Method for making a design layout of a semiconductor integrated circuit

Abstract

A method for designing a semiconductor integrated circuit is provided which comprises compacting a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern, predicting a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern, obtaining an evaluated value by comparing the predicted pattern with the compacted pattern, deciding whether the evaluated value satisfies a predetermined condition, and modifying the design rule when the evaluated value is decided as not satisfying the predetermined condition.

1. A method for designing a semiconductor integrated circuit, comprising:
 compacting a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern;   predicting a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern;   obtaining an evaluated value by comparing the predicted pattern with the compacted pattern;   deciding whether the evaluated value satisfies a predetermined condition; and   modifying the design rule when the evaluated value is decided as not satisfying the predetermined condition.   
     
     
       2. A method according to  claim 1 , wherein the pattern formed at a surface area of a wafer is predicted using data obtained by converting data of the compacted pattern to mask data for photolithography or data for electron beam lithography. 
     
     
       3. A method according to  claim 1 , wherein the pattern formed at a surface area of a wafer is predicted using at least one model selected from a first prediction model, second prediction model and third prediction model, the first prediction model being a model for calculating a light exposed state of a resist on the wafer when the compacted pattern is projected on the resist, the second prediction model being a model for calculating a resist pattern configuration after the resist has been developed, and the third prediction model being a model for calculating a wafer surface configuration after the wafer has been work-processed using the resist pattern. 
     
     
       4. A system for designing a semiconductor integrated circuit, comprising:
 means for compacting a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern;   means for predicting a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern;   means for obtaining an evaluated value by comparing the predicted pattern with the compacted pattern;   means for deciding whether the evaluated value satisfies a predetermined condition; and   means for modifying the design rule when the evaluated value is decided as not satisfying the predetermined condition.   
     
     
       5. A system according to  claim 4 , wherein the pattern formed at a surface area of a wafer is predicted using data obtained by converting data of the compacted pattern to mask data for lithography or data for electron beam lithography. 
     
     
       6. A system according to  claim 4 , wherein the pattern formed at a surface area of a wafer is predicted using at least one model selected from a first prediction model, second prediction model and third prediction model, the first prediction model being a model for calculating a light exposed state of a resist on the wafer when the compacted pattern is projected on the resist, the second prediction model being a model for calculating a resist pattern configuration after the resist has been developed, and the third prediction model being a model for calculating a wafer surface configuration after the wafer has been work-processed using the resist pattern. 
     
     
       7. A computer readable medium configured to store program instructions for causing a computer to compact a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern, causing the computer to predict a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern, causing the computer to obtain an evaluated value by comparing the predicted pattern with the compacted pattern, causing the computer to decide whether the evaluated value satisfies a predetermined condition, and causing the computer to modify the design rule when the evaluated value is decided as not satisfying the predetermined condition. 
     
     
       8. A method for making a design layout of a semiconductor integrated circuit, executed by a computer programmed to perform the method, the method comprising:
 executing the design layout, using a computer, by obtaining a pattern on the basis of a given design rule;   determining a predicted pattern to be formed at a surface area of a wafer, using a computer, on the basis of the design layout;   obtaining an evaluated value, using a computer, by comparing the predicted pattern with the design layout;   determining, using a computer, whether the evaluated value satisfies a predetermined condition; and   modifying the design layout, using a computer, when the evaluated value does not satisfy the predetermined condition.   
     
     
       9. A method for preparing an actual mask for a semiconductor integrated circuit, comprising:
 preparing a design layout by obtaining a pattern on the basis of a given design rule;   determining a predicted pattern to be formed at a surface area of a wafer on the basis of the design layout;   obtaining an evaluated value by comparing the predicted pattern with the design layout;   determining whether the evaluated value satisfies a predetermined condition;   modifying the design layout when the evaluated value does not satisfy the predetermined condition; and   preparing an actual mask using the modified design layout.   
     
     
       10. A method for making a design layout of a semiconductor integrated circuit, executed by a computer programmed to perform the method, the method comprising:
 preparing an extracted design rule by performing a test, using a computer;   executing the design layout, using a computer, by obtaining a pattern on the basis of the extracted design rule;   determining a predicted pattern to be formed at a surface area of a wafer, using a computer, on the basis of the design layout;   obtaining an evaluated value, using a computer, by comparing the predicted pattern with the design layout,   determining, using a computer, whether the evaluated value satisfies a predetermined condition; and   modifying the design layout, using a computer, when the evaluated value does not satisfy the predetermined condition.   
     
     
       11. A method for manufacturing a semiconductor device, comprising:
 forming a circuit pattern on a semiconductor wafer based on the design layout made by the method according to claim 8.   
     
     
       12. A non-transitory computer readable storage medium encoded with a computer program product storing program instructions for causing a computer to perform the method according to claim 8. 
     
     
       13. A method according to claim 8, wherein the design layout includes an OPC data.