Integrated circuit device having stacked dies and impedance balanced transmission lines

Abstract

A multi-chip device which includes a plurality of integrated circuit die disposed one over another. Each integrated circuit die includes one or a plurality of bond pads. One or a plurality of conductors are disposed to electrically couple the bond pads of vertically adjacent integrated circuit die. Each conductor is designed, calculated, specified and/or predetermined to have a length so as to behave as a segment in a multi-drop transmission line. The multi-drop transmission line may be terminated at one end or utilized in a flow-through approach. In one embodiment, an integrated circuit die may be horizontally offset with respect to a vertically adjacent integrated circuit die to expose the periphery region. In another embodiment, each integrated circuit die may be stacked and aligned in a vertical column. In this embodiment, a spacer such as a thermally conductive spacer is disposed between each integrated circuit die in the stack. In yet another embodiment, two or more stacks of integrated circuit die are disposed in the multi-chip device and the one or more multi-drop transmission lines may be implemented in the flow-through approach. The plurality of integrated circuit die may comprise a plurality of memory devices, or a plurality of memory devices and a controller, or a plurality of controllers and a plurality of memory devices.

1. An integrated circuit (IC) device, comprising:
 a substrate connecting connected to an external transmission line having a first impedance; 
 a plurality of IC dies arranged in a stacked configuration on the substrate; 
 a termination element having a second impedance; and 
 a multi-drop transmission line connecting bond pads associated with selected ones of the plurality of IC dies between the external transmission line and the termination element, wherein the multi-drop transmission line has a third impedance matched to at least one of the first and second impedances. 
 
     
     
       2. The IC device of  claim 1 , wherein the third impedance matches at least one of the first and second impedances by a percentage in a range of from 70 percent to 130 percent. 
     
     
       3. The IC device of  claim 1 , further comprising an impedance matching stub line connected to the at least one of the external transmission line and the multi-drop transmission line. 
     
     
       4. The IC device of  claim 1 , wherein the plurality of IC dies comprises a first vertical stack of IC dies and a separate, second vertical stack of IC dies. 
     
     
       5. An integrated circuit (IC) device comprising:
 an external transmission line having a first impedance; 
 a plurality of IC dies arranged in a stacked configuration; and 
 a multi-drop transmission line having a second impedance and electrically connecting the plurality of the IC dies to the external transmission line, wherein the second impedance is matched to the first impedance. 
 
     
     
       6. The IC device of  claim 5 , wherein the external transmission line comprises a first segment having the first impedance and second segment having a third impedance; and
 wherein the multi-drop transmission line is connected in parallel with the second segment of the external transmission line such that the effective impedance of the parallel combination is matched to the first impedance. 
 
     
     
       7. The integrated circuit device of  claim 1 , wherein the multi-drop transmission line further comprises:
 a first transmission line segment connecting the external transmission line and a first bond pad on a first IC die of the plurality IC dies; 
 a second transmission line segment connecting the first bond pad and a second bond pad on a second IC die of the plurality of IC dies; and, 
 a third transmission line segment connecting to the terminal termination element to a respective bond pad on an IC die of the plurality of IC dies other than the first IC die. 
 
     
     
       8. The integrated circuit device of  claim 1 , wherein the multi-drop transmission line comprises at least one bond wire and a flex tape. 
     
     
       9. The integrated circuit device of  claim 1 , including:
 a plurality of multi-drop transmission lines; 
 a first plurality of pads disposed on a first IC die of the plurality of IC dies, wherein each pad of the first plurality of pads is electrically connected to a respective multi-drop transmission line of the plurality of multi-drop transmission lines; and 
 a second plurality of pads disposed on a second IC die of the plurality of IC dies, wherein each pad of the second plurality of pads is electrically connected to a respective multi-drop transmission line of the plurality of transmission lines. 
 
     
     
       10. The integrated circuit device of  claim 1 , further comprising:
 a first principal surface of the substrate mounting a first IC die of the plurality of IC dies, and a second principal surface of the substrate opposite the first principal surface comprising a ball grid array; 
 wherein the multi-drop transmission line is electrically connected to the external transmission line through a portion of the ball grid array. 
 
     
     
       11. The integrated circuit device of  claim 1 , the multi-drop transmission line comprising a first transmission line, and the wherein the bond pads connecting connect to the first transmission line comprising respective first bond pads; the integrated circuit device further comprising:
 a second transmission line having a fourth impedance connecting at least a second bond pad on a respective IC die of the plurality of IC dies between a second an external bus having a fifth impedance and a second termination element having a sixth impedance, wherein the fourth impedance is matched with at least one of the fifth impedance and sixth impedance. 
 
     
     
       12. The integrated circuit device of  claim 11 , wherein the external transmission line is a first external transmission line, the integrated circuit device further comprising:
 a first principal surface of the substrate mounting a first IC die of the plurality of IC dies, and a second principal surface of the substrate opposite the first principal surface comprising a ball grid array; 
 wherein first transmission line is electrically connected to the first external transmission line through a first portion of the ball grid array and the second transmission line connects to the second external transmission line via a second portion of the ball grid array. 
 
     
     
       13. The integrated circuit device of  claim 1 , wherein the termination element is a resistor electrically connected between an end of the multi-drop transmission line and a voltage terminal. 
     
     
       14. The integrated circuit device of  claim 1 , wherein a resistance value for the termination element is matched to the third impedance. 
     
     
       15. The integrated circuit device of  claim 1 , further comprising a plurality of spacers, wherein each spacer is disposed between vertically adjacent IC dies of the plurality of IC dies, and wherein the plurality of IC dies and the plurality of spacers are encapsulated. 
     
     
       16. The integrated circuit device of  claim 15 , wherein the multi-drop transmission line comprises a plurality of segments, a first segment connecting the external bus to a first bond pad on a first IC die in the plurality of IC dies, additional segments respectively connecting bond pads between the vertically adjacent IC dies, and a final segment connecting a first bond pad on a last IC die in the plurality of IC dies to the termination element. 
     
     
       17. The integrated circuit device of  claim 1 , wherein a first IC die in the plurality of IC dies is a controller and at least one of the other IC dies in the plurality of IC dies is a memory device. 
     
     
       18. The integrated circuit device of  claim 1 , wherein an edge of a first IC die of the plurality of IC dies is offset with respect to an edge of a second IC die of the plurality of IC dies to expose a periphery region on the first IC die, and wherein a first conductive pad on the first IC die is disposed at the periphery region. 
     
     
       19. The integrated circuit device of claim 1, wherein the integrated circuit device is a multi-chip device. 
     
     
       20. The integrated circuit device of claim 1, wherein the external transmission line is external to the plurality of IC dies. 
     
     
       21. The integrated circuit device of claim 1, wherein the first impedance, the second impedance, and the third impedance each comprise a characteristic impedance. 
     
     
       22. The integrated circuit device of claim 1, wherein at least one of the first and second impedances match the third impedance by a percentage in a range of 70 percent to 130 percent. 
     
     
       23. The integrated circuit device of claim 5, wherein the integrated circuit device is a multi-chip device. 
     
     
       24. The integrated circuit device of claim 5, wherein the external transmission line is external to the plurality of IC dies. 
     
     
       25. The integrated circuit device of claim 5, wherein the first impedance, and the second impedance each comprise a characteristic impedance. 
     
     
       26. The integrated circuit device of claim 5, wherein the first impedance matches the second impedance by a percentage in a range of 70 percent to 130 percent. 
     
     
       27. The integrated circuit device of claim 5, wherein the external transmission line is coupled to a substrate. 
     
     
       28. The integrated circuit device of claim 5, further comprising an impedance matching stub line connected to the multi-drop transmission line. 
     
     
       29. The integrated circuit device of claim 5, wherein the plurality of IC dies comprises a first vertical stack of IC dies and a separate, second vertical stack of IC dies. 
     
     
       30. The integrated circuit device of claim 5, wherein the multi-drop transmission line includes a termination element. 
     
     
       31. The integrated circuit device of claim 30, wherein the multi-drop transmission line further comprises:
 a first transmission line segment connecting the external transmission line and a first bond pad on a first IC die of the plurality IC dies;   a second transmission line segment connecting the first bond pad and a second bond pad on a second IC die of the plurality of IC dies; and,   a third transmission line segment connecting the termination element and a respective bond pad on an IC die of the plurality of IC dies other than the first IC die.   
     
     
       32. The integrated circuit device of claim 30, wherein the termination element is a resistor electrically connected between an end of the multi-drop transmission line and a voltage terminal. 
     
     
       33. The integrated circuit device of claim 30, wherein a resistance value for the termination element is matched to the first impedance. 
     
     
       34. The integrated circuit device of claim 30, wherein the multi-drop transmission line comprises a plurality of segments, a first segment connecting the external bus to a first bond pad on a first IC die in the plurality of IC dies, additional segments respectively connecting bond pads between vertically adjacent IC dies, and a final segment connecting a first bond pad on a last IC die in the plurality of IC dies to the termination element. 
     
     
       35. The integrated circuit device of claim 5, wherein the multi-drop transmission line comprises at least one bond wire and a flex tape. 
     
     
       36. The integrated circuit device of claim 5, including:
 a plurality of multi-drop transmission lines;   a first plurality of pads disposed on a first IC die of the plurality of IC dies, wherein each pad of the first plurality of pads is electrically connected to a respective multi-drop transmission line of the plurality of multi-drop transmission lines; and   a second plurality of pads disposed on a second IC die of the plurality of IC dies, wherein each pad of the second plurality of pads is electrically connected to a respective multi-drop transmission line of the plurality of multi-drop transmission lines.   
     
     
       37. The integrated circuit device of claim 5, further comprising:
 a first principal surface of the substrate mounting a first IC die of the plurality of IC dies, and a second principal surface of the substrate opposite the first principal surface comprising a ball grid array;   wherein the multi-drop transmission line is electrically connected to the external transmission line through a portion of the ball grid array.   
     
     
       38. The integrated circuit device of claim 5, further comprising a plurality of spacers, wherein each spacer is disposed between vertically adjacent IC dies of the plurality of IC dies. 
     
     
       39. The integrated circuit device of claim 5, wherein a first IC die in the plurality of IC dies is a controller and at least one of the other IC dies in the plurality of IC dies is a memory device. 
     
     
       40. The integrated circuit device of claim 5, wherein an edge of a first IC die of the plurality of IC dies is offset with respect to an edge of a second IC die of the plurality of IC dies to expose a periphery region on the first IC die, and wherein a first conductive pad on the first IC die is disposed at the periphery region. 
     
     
       41. A semiconductor module, comprising:
 a plurality of IC dies stacked one on top of another;   a termination element electrically coupled to at least one of the plurality of IC dies, wherein the termination element has a first impedance; and   a multi-drop transmission line electrically coupling at least two of the plurality of IC die to one another, wherein the multi-drop transmission line has a second impedance, and wherein the first impedance and the second impedance are substantially matched.   
     
     
       42. The semiconductor module of claim 41, wherein the plurality of IC dies are stacked one on top of another from a first IC die to a final IC die, wherein the termination element is electrically coupled to the final IC die. 
     
     
       43. The semiconductor module of claim 41 wherein the plurality of IC dies are stacked one on top of another from a first IC die to a final IC die, wherein the termination element is mechanically and electrically coupled to the final IC die. 
     
     
       44. The semiconductor module of claim 41, wherein the plurality of IC dies are stacked one on top of another from a first IC die to a final IC die, and further comprising at least one electrical connector electrically coupled to the first IC die, wherein the at least one electrical connector has a third impedance. 
     
     
       45. The semiconductor module of claim 44, wherein the first impedance, the second impedance, and the third impedance are substantially matched. 
     
     
       46. The semiconductor module of claim 44, wherein the at least one electrical connector and the first IC die are coupled to a substrate. 
     
     
       47. The semiconductor module of claim 44, wherein the third impedance is matched to the first impedance, the second impedance, or both the first impedance and the second impedance. 
     
     
       48. The semiconductor module of claim 44, wherein the third impedance is matched to the second impedance by a percentage in a range of 70 percent to 130 percent. 
     
     
       49. The semiconductor module of claim 41, further comprising an impedance matching stub line connected to the at least one of an external transmission line and the multi-drop transmission line. 
     
     
       50. The semiconductor module of claim 41, wherein the plurality of IC dies comprises a first vertical stack of IC dies and a separate, second vertical stack of IC dies. 
     
     
       51. The semiconductor module of claim 41, wherein the multi-drop transmission line further comprises:
 a first transmission line segment connecting a first bond pad on a first IC die of the plurality IC dies to an electrical connector;   a second transmission line segment connecting the first bond pad and a second bond pad on a second IC die of the plurality of IC dies; and,   a third transmission line segment connecting the termination element to a respective bond pad on an IC die of the plurality of IC dies other than the first IC die.   
     
     
       52. The semiconductor module of claim 41, wherein the multi-drop transmission line includes a bond wire, a flex tape, or a bond wire and a flex tape. 
     
     
       53. The semiconductor module of claim 41, including:
 a plurality of multi-drop transmission lines;   a first plurality of pads disposed on a first IC die of the plurality of IC dies, wherein each pad of the first plurality of pads is electrically connected to a respective multi-drop transmission line of the plurality of multi-drop transmission lines; and   a second plurality of pads disposed on a second IC die of the plurality of IC dies, wherein each pad of the second plurality of pads is electrically connected to a respective multi-drop transmission line of the plurality of transmission lines.   
     
     
       54. The semiconductor module of claim 41, further comprising:
 a substrate having a substantially flat first surface and an opposing substantially flat second surface;   a ball grid array of connectors coupled to the second surface;   a first IC die of the plurality of IC dies coupled to the first surface, wherein the multi-drop transmission line is electrically connected to at least a portion of the ball grid array.   
     
     
       55. The semiconductor module of claim 41, wherein the termination element is a resistor electrically connected between an end of the multi-drop transmission line and a voltage terminal. 
     
     
       56. The semiconductor module of claim 41, wherein the second impedance is a characteristic impedance of the multi-drop transmission line, and a resistance value of the termination element substantially matches the characteristic impedance of the multi-drop transmission line. 
     
     
       57. The semiconductor module of claim 41, further comprising a plurality of spacers, wherein each spacer is disposed between vertically adjacent IC dies of the plurality of IC dies. 
     
     
       58. The semiconductor module of claim 41, wherein the plurality of IC dies, termination element, and multi-drop transmission line are housed in a single package. 
     
     
       59. The semiconductor module of claim 41, wherein a first IC die in the plurality of IC dies is a controller and at least one of the other IC dies in the plurality of IC dies is a memory device. 
     
     
       60. The semiconductor module of claim 41, wherein an edge of a first IC die of the plurality of IC dies is offset with respect to an edge of a second IC die of the plurality of IC dies to expose a periphery region on the first IC die, and wherein a first conductive pad on the first IC die is disposed at the periphery region. 
     
     
       61. A semiconductor package, comprising:
 a plurality of IC dies disposed substantially adjacent one another;   a termination element electrically coupled to at least one of the plurality of IC dies, wherein the termination element has a first impedance; and   a multi-drop transmission line electrically coupled to the plurality of IC die, wherein the multi-drop transmission line has a second impedance, and wherein the first impedance and the second impedance are substantially matched.   
     
     
       62. The semiconductor package of claim 61, wherein the first impedance and the second impedance are matched to be within a predetermined range of each other. 
     
     
       63. The semiconductor package of claim 61, wherein the first impedance is matched to the second impedance by a percentage in a range of 70 percent to 130 percent. 
     
     
       64. The semiconductor package of claim 61, further comprising an impedance matching stub line connected to the at least one of an external transmission line and the multi-drop transmission line. 
     
     
       65. The semiconductor package of claim 61, wherein the plurality of IC dies are mounted substantially coplanar to one another on a substrate. 
     
     
       66. The semiconductor package of claim 61, wherein the multi-drop transmission line further comprises:
 a first transmission line segment connecting a first bond pad on a first IC die of the plurality IC dies to an electrical connector;   a second transmission line segment connecting the first bond pad and a second bond pad on a second IC die of the plurality of IC dies; and,   a third transmission line segment connecting the termination element to a respective bond pad on an IC die of the plurality of IC dies other than the first IC die.   
     
     
       67. The semiconductor package of claim 61, wherein the multi-drop transmission line includes a bond wire, a flex tape, or a bond wire and a flex tape. 
     
     
       68. The semiconductor package of claim 61, including:
 a plurality of multi-drop transmission lines;   a first plurality of pads disposed on a first IC die of the plurality of IC dies, wherein each pad of the first plurality of pads is electrically connected to a respective multi-drop transmission line of the plurality of multi-drop transmission lines; and   a second plurality of pads disposed on a second IC die of the plurality of IC dies, wherein each pad of the second plurality of pads is electrically connected to a respective multi-drop transmission line of the plurality of transmission lines.   
     
     
       69. The semiconductor package of claim 61, further comprising:
 a substrate having a substantially flat first surface and an opposing substantially flat second surface;   a ball grid array of connectors coupled to the second surface, wherein the plurality of IC dies are coupled to the first surface, and wherein the multi-drop transmission line is electrically connected to at least a portion of the ball grid array.   
     
     
       70. The semiconductor package of claim 61, wherein the termination element is a resistor electrically connected between an end of the multi-drop transmission line and a voltage terminal. 
     
     
       71. The semiconductor package of claim 61, wherein a resistance value for the termination element is selected to reduce signal reflections. 
     
     
       72. The semiconductor package of claim 61, wherein the plurality of IC dies, termination element, and multi-drop transmission line are housed in a single package. 
     
     
       73. The semiconductor package of claim 61, wherein a first IC die in the plurality of IC dies is a controller and at least one of the other IC dies in the plurality of IC dies is a memory device. 
     
     
       74. The semiconductor package of claim 61, wherein said plurality of IC dies include a controller and multiple memory devices. 
     
     
       75. The semiconductor package of claim 74, further comprising additional termination elements, where each termination element is electrically coupled to a respective one of said memory devices. 
     
     
       76. The semiconductor package of claim 74, further comprising additional termination elements, where each termination element is mechanically coupled to a respective one of said memory devices. 
     
     
       77. A semiconductor package, comprising:
 a plurality of IC dies stacked one on top of another;   a termination element electrically coupled to at least one of the plurality of IC dies, wherein the termination element has a first impedance; and   a multi-drop transmission line electrically coupled to at least two of the plurality of IC die, wherein the multi-drop transmission line has a second impedance, and wherein the first impedance and the second impedance are selected to reduce signal reflections.   
     
     
       78. A semiconductor package, comprising:
 a plurality of IC dies disposed substantially adjacent one another;   a termination element electrically coupled to at least one of the plurality of IC dies, wherein the termination element has a first impedance; and   a multi-drop transmission line electrically coupled to at least two of the plurality of IC die, wherein the multi-drop transmission line has a second impedance, and wherein the first impedance and the second impedance are selected to reduce signal reflections.   
     
     
       79. A semiconductor package, comprising:
 a plurality of IC dies stacked one on top of another;   a termination element electrically coupled to at least one of the plurality of IC dies, wherein the termination element has a first impedance; and   a multi-drop transmission line electrically coupling at least two of the plurality of IC die to one another, wherein the multi-drop transmission line has a second impedance, and wherein the first impedance and the second impedance are matched to be within a predetermined range of each other.   
     
     
       80. A multi-chip device comprising:
 a plurality of IC dies arranged in a stacked configuration, at least one of the plurality of IC dies having an on-chip termination element, wherein the on-chip termination element has a first impedance; and   a multi-drop transmission line electrically coupled to at least two of the plurality of IC dies, wherein the multi-drop transmission line has a second impedance, and wherein the first impedance is matched to be in the range of between 70 and 130 percent of the second impedance.   
     
     
       81. The multi-chip device of claim 80, wherein the plurality of IC dies comprise a plurality of memory dies. 
     
     
       82. The multi-chip device of claim 81, wherein each of the plurality of memory dies includes an on-chip termination element. 
     
     
       83. The multi-chip device of claim 80, wherein the plurality of IC dies comprise a controller die and at least one memory die. 
     
     
       84. The multi-chip device of claim 82, wherein the on-chip termination element is implemented on the at least one memory die. 
     
     
       85. A multi-chip package comprising:
 a substrate having a connector to be coupled to an external transmission line with a characteristic impedance;   a plurality of IC dies disposed in a stacked configuration on the substrate, at least one of the plurality of IC dies including an on-chip termination element;   an internal transmission line coupled to the plurality of IC dies and having one end coupled to the connector, the internal transmission line including a segment terminating at the on-chip termination element and having an impedance in a range of between 70 and 130 percent of the characteristic impedance.   
     
     
       86. The multi-chip package of claim 85, wherein the connector comprises a ball bond. 
     
     
       87. A multi-chip package comprising:
 a substrate having a connector to be coupled to an external transmission line;   an internal transmission line having one end coupled to the connector, the internal transmission line having a first characteristic impedance;   a first IC die coupled to the internal transmission line;   a second IC die including an on-chip termination element coupled to the internal transmission line, the on-chip termination element comprising an impedance having a value within the range of between 70 and 130 percent of the first characteristic impedance.   
     
     
       88. The multi-chip package of claim 87, wherein the substrate comprises a ball grid array substrate. 
     
     
       89. The multi-chip package of claim 87, wherein the substrate comprises a flexible substrate. 
     
     
       90. The multi-chip package of claim 89, wherein the substrate comprises flex tape. 
     
     
       91. The multi-chip package of claim 87, wherein the connector comprises a ball bond. 
     
     
       92. The multi-chip package of claim 87, wherein the connector comprises a lead. 
     
     
       93. The multi-chip package of claim 87, wherein the external transmission line has a second characteristic impedance, the second characteristic impedance having a value within the range of between 70 and 130 percent of the first characteristic impedance. 
     
     
       94. A memory system comprising:
 a controller integrated circuit (IC) die;   a first memory IC die disposed adjacent to the controller IC die, the memory IC die including an on-chip termination element having a first impedance;   a transmission line coupled to the controller IC die and the on-chip termination element, the transmission line having a characteristic impedance, wherein the first impedance is within 70 to 130 percent of the value of the characteristic impedance.   
     
     
       95. The memory system of claim 94, wherein the controller IC die and the memory IC die are disposed in a semiconductor package. 
     
     
       96. The memory system of claim 95, wherein the transmission line is disposed internal to the semiconductor package. 
     
     
       97. The memory system of claim 94, wherein the memory IC die is disposed adjacent to the controller IC die in a stacked configuration. 
     
     
       98. The memory system of claim 94, and further including a second memory die coupled to the transmission line. 
     
     
       99. The memory system of claim 98, wherein the transmission line comprises a multi-drop transmission line. 
     
     
       100. The memory system of claim 94, wherein the controller IC die and the memory IC die are disposed in a stacked configuration on a substrate. 
     
     
       101. The memory system of claim 100, wherein the substrate comprises a ball grid array substrate.