Stacked semiconductor module

Abstract

The semiconductor module is provided that includes a semiconductor housing and a plurality of integrated circuit dice positioned within the housing. The semiconductor module also includes a programmable memory device positioned within the housing and electrically coupled to the plurality of integrated circuit dice. The programmable memory device is programmable to identify the integrated circuit dice that meet a predetermined standard, such as an operating frequency requirement, or a core timing grade. Further, a method is provided for accessing a semiconductor module. The above mentioned housing is provided to enclose the plurality of integrated circuit dice and the programmable memory device. The integrated circuit dice of the plurality of integrated circuit dice that meet a predetermined standard are then identified. The programmable memory device is subsequently programmed to identify the selected integrated circuit dice.

1. A method of operation of a module that includes a plurality of integrated circuit memory devices and a programmable memory device disposed within a housing, wherein the method comprises:
 determining a core timing grade for each of said plurality of integrated circuit memory devices; 
 identifying which core timing grade is a lowest core timing grade; and 
 storing in the programmable memory device, the lowest core timing grade as a maximum core timing grade for the module. 
 
     
     
       2. The method according to  claim 1 , wherein said determining only occurs for those integrated circuit memory devices of said plurality of integrated circuit memory devices that function. 
     
     
       3. The method according to  claim 1 , wherein said identifying only occurs for those integrated circuit memory devices of said plurality of integrated circuit memory devices that meet a threshold core timing grade. 
     
     
       4. The method according to  claim 1 , wherein said storing comprises programming fuses, a read only memory (ROM) integrated circuit chip, a read/write integrated circuit chip, or an erasable programmable read-only memory (EPROM). 
     
     
       5. A method of operation of a memory module that includes a plurality of integrated circuit memory devices and a programmable memory device disposed within a housing, wherein the method comprises storing in the programmable memory device a lowest core timing grade, of all core timing grades of the plurality of integrated circuit memory devices, as a maximum core timing grade for the memory module. 
     
     
       6. A method of operation of a module that includes a plurality of integrated circuit memory devices and a programmable memory device disposed within a housing, wherein the method comprises:
 determining a value of an operating characteristic for each of said plurality of integrated circuit memory devices;   identifying which value meets a predefined criteria; and   storing in the programmable memory device, the value that meets the predefined criteria as an operating constraint for the module.    
     
     
       7. The method according to claim 6, wherein the determining comprises:
 determining a core timing grade for each of said plurality of integrated circuit memory devices.    
     
     
       8. The method according to claim 7, wherein the identifying comprises:
 identifying which core timing grade is a lowest core timing grade.    
     
     
       9. The method according to claim 8, wherein the storing comprises:
 storing in the programmable memory device, the lowest core timing grade as a maximum core timing grade for the module.    
     
     
       10. The method according to claim 6, wherein the operating characteristic is selected from a group consisting of: core timing grade and operating frequency.  
     
     
       11. The method according to claim 6, wherein the operating constraint is selected from a group consisting of: a maximum core timing grade of the module and a maximum operating frequency of the module.  
     
     
       12. The method according to claim 6, wherein identifying which value meets the predefined criteria includes selecting a lowest value of the plurality of values.  
     
     
       13. The method according to claim 6, wherein said determining only occurs for those integrated circuit memory devices of said plurality of integrated circuit memory devices that function.  
     
     
       14. The method according to claim 6, wherein said identifying only occurs for those integrated circuit memory devices of said plurality of integrated circuit memory devices that have a value for the operating characteristic that meets a predefined threshold.  
     
     
       15. The method according to claim 6, wherein said storing comprises programming fuses, a read only memory (ROM) integrated circuit chip, a read/write integrated circuit chip, or an erasable programmable read-only memory (EPROM).  
     
     
       16. The method according to claim 6, further comprising:
 determining which integrated circuit device of the plurality of integrated circuit devices meet a predetermined standard; and   storing in the programmable memory device an identification of those integrated circuit dies that meet the predetermined standard.    
     
     
       17. The method according to claim 16, wherein the predetermined standard for each of the integrated circuit devices is whether that integrated circuit device is functional or meets a predefined threshold.  
     
     
       18. A method of operation of a module that includes a plurality of integrated circuit memory devices and a programmable memory device disposed within a housing, wherein the method comprises:
 determining a plurality of values of an operating characteristic, the plurality of values including a value of the operating characteristic for each of said plurality of integrated circuit memory devices;   identifying a respective value of the plurality of values in accordance with predefined criteria; and   storing in the programmable memory device, the respective value as an operating constraint for the module.    
     
     
       19. The method according to claim 18, wherein determining the plurality of values of the operating characteristic includes:
 determining a core timing grade for each of said plurality of integrated circuit memory devices.    
     
     
       20. The method according to claim 18, wherein identifying the respective value of the plurality of values in accordance with the predefined criteria includes:
 identifying which core timing grade is a lowest core timing grade.    
     
     
       21. The method according to claim 18, wherein storing in the programmable memory device, the respective value as an operating constraint for the module includes:
 storing in the programmable memory device, the lowest core timing grade as a maximum core timing grade for the module.    
     
     
       22. A method of operation of a module that includes a plurality of integrated circuit memory devices and a programmable memory device disposed within a housing, wherein the method comprises:
 determining which integrated circuit device of the plurality of integrated circuit devices meet a predetermined standard;   storing in the programmable memory device an identification of those integrated circuit dies that meet the predetermined standard;   determining information related to an operating characteristic for each of said plurality of integrated circuit memory devices;   identifying which information meets a predefined criteria; and   storing in the programmable memory device, the information that meets the predefined criteria as an operating constraint for the module.