Semiconductor memory device for controlling write recovery time

Abstract

A semiconductor memory device includes a CAS latency mode detecting means for outputting a CAS latency control signal in response to a CAS latency mode; and an auto-precharge control means for controlling timing of an auto-precharge operation in response to the CAS latency control signal.

What is claimed is: 
     
       1. A semiconductor memory device capable of controlling a timing of an auto-precharge operation, comprising:
 a CAS latency mode detecting means for outputting a CAS latency control signal in response to a CAS latency mode; and 
 an auto-precharge control means for controlling the timing of an auto-precharge operation in response to the CAS latency control signal, wherein the auto-precharge control means includes: 
 an auto-precharge timing decoder for activating one of a plurality of output signals from the auto-precharge timing decoder by decoding the CAS latency control signal and a control signal; and 
 an auto-precharge timing control unit for controlling output timing of an auto-precharge performing signal in response to the activated output signal. 
 
     
     
       2. The semiconductor memory device as recited in  claim 1 , wherein the auto-precharge control means includes:
 a timing control unit for generating the control signal to control timing of the auto-precharge operation. 
 
     
     
       3. The semiconductor memory device as recited in  claim 2 , wherein the timing control unit includes a plurality of fuses and outputs the control signal by selectively blowing the plurality of fuses. 
     
     
       4. The semiconductor memory device as recited in  claim 2 , wherein the CAS latency mode detecting means includes a plurality of unit CAS latency mode detectors, each for selectively activating and outputting the CAS latency control signal according to the GAS CAS latency mode. 
     
     
       5. The semiconductor memory device as recited in  claim 4 , wherein each of the plurality of unit GAS CAS latency mode detectors includes a logic gate for performing a logic operation to two GAS CAS latency modes for outputting the resultant of the logic operation. 
     
     
       6. The semiconductor memory device as recited in  claim 2 , wherein the auto-precharge timing decoder includes:
 an internal decoder for decoding the control signal; and 
 a signal mixing unit for performing a logic operation to a plurality of signals outputted from the internal decoder and the GAS CAS latency mode control signal to output the resultant of the logic operation. 
 
     
     
       7. The semiconductor memory device as recited in  claim 6 , wherein the auto-precharge timing control unit includes:
 a delay means including a plurality of unit delays for delaying the auto-precharge performing signal depending on the plurality of output signals from the auto-precharge timing decoder; and 
 a signal output unit which receives the auto-precharge performing signal and an output signal from the delay means for outputting the auto-precharge performing signal when all of the plurality of output signals from the auto-precharge timing decoder are inactivated and for outputting the output signal from the delay means when one of the plurality of output signals from the auto-precharge timing decoder is activated. 
 
     
     
       8. The semiconductor memory device as recited in  claim 7 , wherein the delay means includes:
 a first unit delay for delaying the auto-precharge performing signal; 
 a first transferring gate turned on by a first output signal among outputted signals from the auto-precharge timing decoder for transferring an output signal from the first unit delay; 
 a second unit delay for delaying an output signal from the first unit delay; 
 a second transferring gate turned on by a second output signal among outputted signals from the auto-precharge timing decoder for transferring an output signal from the second unit delay; 
 a third unit delay for delaying an output signal from the second unit delay; 
 a third transferring gate turned on by a third output signal among outputted signals from the auto-precharge timing decoder for transferring an output signal from the third unit delay; 
 a fourth unit delay for delaying an output signal from the third unit delay; 
 a fourth transferring gate turned on by a fourth output signal among outputted signals from the auto-precharge timing decoder for transferring an output signal from the fourth unit delay; and 
 a latch for latching an output signal from the first to fourth transferring gates. 
 
     
     
       9. The semiconductor memory device as recited in  claim 7 , the signal output unit includes:
 a logic gate for performing a logic operation to the plurality of output signals from the auto-precharge timing decoder; 
 a first transferring gate which is turned on when an output signal from the logic gate is in a logic low level to output the auto-precharge performing signal; and 
 a second transferring gate which is turned on when the output signal from the logic gate is in a logic high level to output the output signal from the delay means. 
 
     
     
       10. A method of controlling timing of a precharge operation according to a CAS latency mode, the method comprising a step of:
 detecting the CAS latency mode; 
 outputting a delay signal corresponding to the CAS latency mode; 
 outputting an a delayed auto-precharge signal after delaying the an auto-precharge signal by passing the auto-precharge signal through one or more unit delays; and 
 performing an auto-precharge operation in response to the delayed auto-precharge signal, wherein the number of the unit delays where the auto-precharge signal passes through is determined by the delay signal. 
 
     
     
       11. A semiconductor memory device, comprising:
 a CAS latency mode detecting means for outputting a CAS latency control signal in response to a CAS latency mode; and 
 an auto-precharge control means for controlling the timing of an auto-precharge operation in response to one of plural signals generated by decoding the CAS latency control signal. 
 
     
     
       12. The semiconductor memory device as recited in  claim 11 , wherein the auto-precharge control means includes:
 a timing control unit for generating a control signal to control timing of the auto-precharge operation; 
 an auto-precharge timing decoder for activating one of a plurality of output signals by decoding the CAS latency control signal and the control signal; and 
 an auto-precharge timing control unit for controlling output timing of an auto-precharge performing signal in response to the activated output signal. 
 
     
     
       13. The semiconductor memory device as recited in  claim 12 , wherein the timing control unit includes a plurality of fuses and outputs the control signal by selectively blowing the plurality of fuses. 
     
     
       14. The semiconductor memory device as recited in  claim 12 , wherein the CAS latency mode detecting means includes a plurality of unit CAS latency mode detectors, each for selectively activating and outputting the GAS CAS latency control signal according to the GAS CAS latency mode. 
     
     
       15. The semiconductor memory device as recited in  claim 14 , wherein each of the plurality of unit CAS latency mode detectors includes a logic gate for performing a logic operation to two CAS latency modes for outputting the resultant of the logic operation. 
     
     
       16. The semiconductor memory device as recited in  claim 12 , wherein the auto-precharge timing decoder includes:
 an internal decoder for decoding the control signal; and 
 a signal mixing unit for performing a logic operation to a plurality of signals outputted from the internal decoder and the CAS latency mode control signal to output the resultant of the logic operation. 
 
     
     
       17. The semiconductor memory device as recited in  claim 16 , wherein the auto-precharge timing control unit includes:
 a delay means including a plurality of unit delays for delaying the auto-precharge performing signal depending on the plurality of output signals from the auto-precharge timing decoder; and 
 a signal output unit which receives the auto-precharge performing signal and an output signal from the delay means for outputting the auto-precharge performing signal when all of the plurality of output signals from the auto-precharge timing decoder are inactivated and for outputting the output signal from the delay means when one of the plurality of output signals from the auto-precharge timing decoder is activated. 
 
     
     
       18. The semiconductor memory device as recited in  claim 17 , wherein the delay means includes:
 a first unit delay for delaying the auto-precharge performing signal; 
 a first transferring gate turned on by a first output signal among outputted signals from the auto-precharge timing decoder for transferring an output signal from the first unit delay; 
 a second unit delay for delaying an output signal from the first unit delay; 
 a second transferring gate turned on by a second output signal among outputted signals from the auto-precharge timing decoder for transferring an output signal from the second unit delay; 
 a third unit delay for delaying an output signal from the second unit delay; 
 a third transferring gate turned on by a third output signal among outputted signals from the auto-precharge timing decoder for transferring an output signal from the third unit delay; 
 a fourth unit delay for delaying an output signal from the third unit delay; 
 a fourth transferring gate turned on by a fourth output signal among outputted signals from the auto-precharge timing decoder for transferring an output signal from the fourth unit delay; and 
 a latch for latching an output signal from the first to fourth transferring gates. 
 
     
     
       19. The semiconductor memory device as recited in  claim 17 , the signal output unit includes:
 a logic gate for performing a logic operation to the plurality of output signals from the auto-precharge timing decoder; 
 a first transferring gate which is turned on when an output signal from the logic gate is in a logic low level to output the auto-precharge performing signal; and 
 a second transferring gate which is turned on when the output signal from the logic gate is in a logic high level to output the output signal from the delay means. 
 
     
     
       20. The method of controlling timing according to claim 10, wherein the delay signal is a plurality of delay signals. 
     
     
       21. The method of controlling timing according to claim 20, wherein the range of CAS latencies covers the range from 2 to 5. 
     
     
       22. The method of controlling timing according to claim 20, wherein the plurality of delay signals correspond to CAS latency 2, 3, 4, and 5. 
     
     
       23. The method of controlling timing according to claim 10, further comprising:
 selectively blowing a fuse during wafer-level test; and   detecting whether the fuse was blown, wherein the number of the unit delays where the auto-precharge signal passes through is determined by the delay signal and whether the fuse was blown.   
     
     
       24. The method of controlling timing according to claim 23, wherein the fuse is a plurality of fuses. 
     
     
       25. The method of controlling timing according to claim 10, wherein the number of the unit delays where the auto-precharge signal passes through is determined by the delay signal and the state of a fuse. 
     
     
       26. The method of controlling timing according to claim 25, wherein the fuse is a plurality of fuses. 
     
     
       27. The method of controlling timing according to claim 10, wherein the one or more unit delays are synchronous delays. 
     
     
       28. The method of controlling timing according to claim 10, wherein the one or more unit delays are asynchronous delays. 
     
     
       29. The method of controlling timing according to claim 10, wherein the one or more unit delays are mixed synchronous and asynchronous delays. 
     
     
       30. The method of controlling timing according to claim 10, wherein the one or more unit delays are a plurality of serially connected unit delays. 
     
     
       31. The method of controlling timing according to claim 30, wherein a first unit delay of the plurality of serially connected unit delays receives the auto-precharge signal and provides a first output signal, and a second unit delay of the plurality of serially connected unit delays receives the first output signal and provides a second output signal. 
     
     
       32. The method of controlling timing according to claim 31, wherein the delay signal comprises a first and second decoded signal and the first output signal is transferred as the delayed auto-precharge signal when the first decoded signal is activated and the second output signal is transferred as the delayed auto-precharge signal when the second decoded signal is activated. 
     
     
       33. The method of controlling timing according to claim 32, wherein the auto-precharge signal is transferred as the delayed auto-precharge signal when the first and second decoded signals are inactivated.