Power device with high switching speed and manufacturing method thereof

Abstract

A power device is formed by a thyristor and by a MOSFET transistor, series-connected between a first and a second current-conduction terminal. The power device moreover has a control terminal connected to an insulated-gate electrode of the MOSFET transistor and receiving a control voltage for turning on/off the device, and a third current-conduction terminal connected to the thyristor for fast extraction of charges during turning-off. Thereby, upon turning off, there are no current tails, and turning off is very fast. The power device does not have parasitic components and consequently has a very high reverse-bias safe-operating area.

The invention claimed: 
     
       1. A power device, comprising:
 a first current-conduction terminal; 
 a second current-conduction terminal; 
 a control terminal configured to receive a control voltage for turning on/turning off said to turn the device on and off; 
 a field-effect transistor coupled to the second current-conduction terminal and having a gate electrode coupled to the control terminal; 
 a thyristor and a field-effect transistor connected in series between coupled to said first current-conduction terminal and said second current-conduction terminal, said the transistor having a gate electrode connected to said control terminal; and 
 a third current-conduction terminal connected coupled to said thyristor and configured to extract charges from said thyristor during turning-off as the device turns off. 
 
     
     
       2. The device according to  claim 1 , wherein said transistor is of a vertical-current flow type. 
     
     
       3. The device according to  claim 1 , wherein the thyristor and transistor comprise a semiconductor body having:
 a first surface and a second surface; 
 a substrate region defined by said first surface: 
 a first base region on top of said substrate region; 
 a second base region on top of said first base region; 
 a first conductive region on top of said second base region and defined by said second surface; 
 a second conductive region; 
 a channel region separating said first conductive region from the second conductive region; and 
 a deep region extending from said second surface to one of said first and second base regions; said gate electrode of said transistor being arranged on top of and being electrically insulated from said second surface of said semiconductor body on top of said channel region; said first current-conduction terminal being connected coupled to said substrate region, said second current-conduction terminal being connected coupled to said second conductive region; and said third current-conduction terminal being connected coupled to said deep region. 
 
     
     
       4. The device according to  claim 3 , wherein said first conductive region is formed by a buried region arranged on top of said second base region, and by an epitaxial region arranged on top of said buried region, said buried region having a same conductivity type and different conductivity level with respect to said epitaxial region. 
     
     
       5. The device according to  claim 4 , wherein said buried region has a greater conductivity than said epitaxial region. 
     
     
       6. The device according to  claim 4 , wherein said buried region has a first width and said second base region has a second width greater than said first width, and said deep region extends laterally with respect to said buried region up to said second base region. 
     
     
       7. The device according to  claim 3 , wherein said first conductive region accommodates a body region forming that forms said channel region and accommodating said the body region accommodates the second conductive region; said deep region extending through said first conductive region. 
     
     
       8. The device according to  claim 7 , wherein said substrate region, said second base region and said body region are of P type, and said first base region, said first conductive region and said second conductive region are of N type. 
     
     
       9. A method, comprising: switching a power device that includes a thyristor and a field-effect transistor connected coupled together in series between a first conduction terminal and a second conduction terminal, said switching including:
 turning on and turning off said power device through a control terminal of said transistor;, the turning off including:  
 wherein said step of turning off comprises extracting electrical charges from said thyristor through a third current-conduction terminal connected coupled to said thyristor. 
 
     
     
       10. The method according to  claim 9 , wherein said step of turning on comprises the power device includes applying a control voltage to said control terminal and supplying an electrical quantity to said third current-conduction terminal. 
     
     
       11. The method according to  claim 10 , wherein said electrical quantity is a current pulse. 
     
     
       12. The method according to  claim 10 , wherein said electrical quantity is a d.c. voltage. 
     
     
       13. The method according to  claim 12 , wherein said step of turning off comprises the power devices includes interrupting application of said d.c. voltage. 
     
     
       14. A method of manufacturing a power device, comprising:
 forming, in a body of semiconductor material, a thyristor and a field-effect transistor connected in series coupled together; 
 forming a first current-conduction terminal on a first surface of said body; 
 forming a second current-conduction terminal on a second surface of said body; and 
 forming a control terminal on top of said second surface of said body; and 
 forming an electric-charge extracting terminal connected coupled to said thyristor. 
 
     
     
       15. The method according to  claim 14 , wherein forming the thyristor and transistor includes:
 providing a substrate of a first conductivity type; 
 forming a first base region of a second conductivity type, on top of said substrate; 
 forming a second base region of said first conductivity type on top of said first base region; 
 forming a first conductive region of said second conductivity type on top of said second base region, said first conductive region forming a top surface of said body; 
 forming a deep region, of said first conductivity type, extending from said top surface as far as one of said first and second base regions; 
 forming at least one second conductive region adjacent to said first conductive region and separated therefrom through a channel region; 
 forming at least one insulated-gate region on top of said top surface and arranged on top of said channel region; and 
 forming said first current-conduction terminal in contact with said substrate, said second current-conduction terminal in contact with said second conductive region, said charge-extraction terminal in contact with said deep region, and said control terminal in contact with said insulated-gate region. 
 
     
     
       16. The method according to  claim 15 , wherein said step of forming a the second conductive region comprises includes forming at least one body region inside said first conductive region and forming said second conductive region inside said body region. 
     
     
       17. The method according to  claim 15 , wherein said step of forming a the first conductive region comprises includes forming a buried region on top of said second base region, and growing an epitaxial region on top of said buried region, said buried region and said epitaxial region having said second conductivity type and different conductivity levels. 
     
     
       18. The method according to  claim 17 , wherein said buried region has greater conductivity than said epitaxial region. 
     
     
       19. The method according to  claim 17 , wherein said buried region has a lower smaller width than said second base region, and said step of the forming a of the deep region comprises includes introducing dopant species through said epitaxial region up to said second base region, laterally with respect to said buried region. 
     
     
       20. The method according to  claim 15 , further comprising the step of thinning said substrate before forming said first current-conduction terminal. 
     
     
       21. A power device, comprising:
 a first current-conduction terminal; 
 a second current-conduction terminal; 
 a control terminal; 
 a thyristor; and 
 a vertical field-effect transistor connected coupled with the thyristor between the first current-conduction terminal and the second current-conduction terminal, the transistor having a gate electrode connected coupled to the control terminal; and 
 a third current-conduction terminal coupled to the thyristor, the third current-conduction terminal being configured to extract charges from the thyristor. 
 
     
     
       22. The device according to  claim 21 , further comprising:
 awherein the third current-conduction terminal connected to the thyristor and extractingis configured to extract the charges from the thyristor during turning-off ofas the device is turned off. 
 
     
     
       23. The device according to  claim 21  wherein the transistor is structured to isolate the thyristor from the first current-conduction terminal when the transistor is off. 
     
     
       24. The device according to  claim 21  wherein the transistor includes:
 a first conduction region positioned in a semiconductor body and connected coupled to the first current-conduction terminal; 
 a channel region positioned in the semiconductor body and below the gate electrode; and 
 a second conduction region positioned in the semiconductor body on an opposite side of the channel region from the first conduction region, 
 wherein the thyristor includes:
 a buried region underlying the second conduction region and isolated from the first current-conduction region terminal by the second conduction region; 
 a first base underlying the buried region; 
 a second base underlying the first base; and 
 a substrate region underlying the second base and connected coupled to the second current-conduction region terminal. 
 
 
     
     
       25. The device according to  claim 24 , further comprising a deep region extending from a surface of the semiconductor body to a portion of the first base that extends laterally with respect to the buried region. 
     
     
       26. The device according to  claim 25 , wherein the deep region laterally surrounds the first and second conduction regions and the channel region. 
     
     
       27. The device according to  claim 21  wherein the channel region includes a body region positioned completely within the second conduction region, the first conduction region being positioned completely within the body region. 
     
     
       28. A power device, comprising:
 a first current-conduction terminal;   a second current-conduction terminal;   a third current-conduction terminal;   a thyristor having:
 a first terminal coupled to the first current-conduction terminal; 
 a second terminal coupled to the third current-conduction terminal, the second terminal configured to extract charges from the thyristor as the device powers off; and 
 a third terminal; 
   a field-effect transistor having:
 a gate terminal configured to receive a control voltage to power on and power off the device; 
 a first conductive terminal coupled to the second current-conduction terminal; and 
 a second conductive terminal coupled to the third terminal of the thyristor. 
   
     
     
       29. The device according to claim 28 wherein:
 the first conductive terminal of the transistor is in a semiconductor body;   a channel region of the transistor is in the semiconductor body below the gate electrode; and   the second conductive terminal of the transistor is in the semiconductor body on an opposite side of the channel region from the first conductive terminal;   a buried region of the thyristor is below the second conductive terminal and is isolated from the second current-conduction terminal by the second conductive terminal;   a first base of the thyristor is below the buried region;   a second base of the thyristor is below the first base; and   a substrate region is below the second base and coupled to the first current-conduction terminal.   
     
     
       30. A power device, comprising:
 a thyristor having a base;   a field-effect transistor having a gate;   a first current-conduction terminal coupled to the thyristor;   a second current-conduction terminal coupled to the transistor;   a third current-conduction terminal coupled to the base of the thyristor and configured to extract charges from the thyristor as the device powers off; and   fourth current-conduction terminal coupled to the gate of the transistor.   
     
     
       31. The device according to claim 30 wherein:
 the second current-conduction terminal of the transistor is coupled to a first conductive region in a semiconductor body;   a channel region of the transistor is in the semiconductor body below the gate electrode; and   a second conductive region of the transistor is in the semiconductor body on an opposite side of the channel region from the first conductive region;   a buried region of the thyristor is below the second conductive region and is isolated from the second current-conduction terminal by the second conductive region;   a first base of the thyristor is below the buried region;   a second base of the thyristor is below the first base; and   a substrate region is below the second base and coupled to the first current-conduction terminal.