Duty cycle correction circuit of delay locked loop and delay locked loop having the duty cycle correction circuit

Abstract

A duty cycle correction circuit and a delay locked loop (DLL) including the duty cycle correction circuit, are capable of controlling their operation in order to correctly analyze the cause of generation of a duty cycle error when the duty cycle error is generated in the DLL. The duty cycle correction circuit selectively outputs to a DLL core duty cycle offset information for controlling a duty cycle of an internal clock signal synchronized to an external clock signal under the control of a switching control signal. The DLL corrects the duty cycle of a reference clock signal according to the duty cycle offset information, thereby outputting a reference clock signal having a 50% duty cycle.

What is claimed is: 
     
       1. A delay locked loop (DLL) comprising:
 a DLL core adapted to receive an external clock signal and to generate an internal clock signal synchronized to the external clock signal; 
 a buffer adapted to buffer the internal clock signal and to output differential reference clock signals; and 
 a duty cycle correction circuit adapted to generate first control signals having desired offsets corresponding to differences in duty cycles of the differential reference clock signals, and to output the first control signals to the DLL core under the control of a switching control signal, 
 wherein the DLL core corrects a duty cycle of the internal clock signal in response to the first control signals, 
 wherein in a duty-cycle error analysis mode, the switching control signal selectively turns on and turns off the duty cycle correction circuit to inhibit output of the first control signals to the DLL core, 
 wherein the duty cycle correction circuit comprises:
 a differential amplifier having first and second input terminals and first and second differential output terminals, and adapted to receive the differential reference clock signals via the first and second input terminals, to amplify the differential reference clock signals, and to output the amplified differential reference clock signals via the first and second differential output terminals; 
 a first transmission circuit connected between the first differential output terminal of the differential amplifier and a first node, and adapted to transmit to the first node a first one of the amplified differential reference clock signals appearing at the first differential output terminal of the differential amplifier; 
 a second transmission circuit connected between the second differential output terminal of the differential amplifier and a second node, and adapted to transmit to the second node a second one of the amplified differential reference clock signals appearing at the second differential output terminal of the differential amplifier; 
 a first storage unit connected between the first node and a ground voltage, and adapted to store a signal of the first node; 
 a second storage unit connected between the second node and the ground voltage and adapted to store a signal of the second node; and 
 a switching circuit connected between the first node and a first input terminal of the DLL core, and connected between the second node and a second input terminal of the DLL core, the switching circuit having a control terminal adapted to receive the switching control signal to selectively provide the signals of the first and second nodes to the first and second input terminals of the DLL core as the first control signals, and 
 
 wherein the first transmission circuit is adapted to provide the first one of the amplified differential reference clock signals to the first node, and the second transmission circuit is adapted to provide the second one of the amplified differential reference clock signals to the second node, while the switching control signal has an activated state and while the switching control signal has a deactivated state. 
 
     
     
       2. The delay locked loop of  claim 1 , wherein the switching circuit comprises:
 a third transmission circuit adapted to transmit the signal of the first node to the DLL core when the switching control signal has the deactivated state; 
 a fourth transmission circuit adapted to transmit the signal of the second node to the DLL core when the switching control signal has the deactivated state; 
 a first pull-down circuit which is connected between the first node and the ground voltage, and pulls down the first node to the ground voltage when the switching control signal has the activated state; and 
 a second pull-down circuit which is connected between the second node and the ground voltage, and pulls down the second node to the ground voltage when the switching control signal has the activated state. 
 
     
     
       3. The delay locked loop of  claim 1 , wherein each of the first and second storage units includes a MOS transistor. 
     
     
       4. A delay locked loop (DLL) comprising:
 a DLL core adapted to receive an external clock signal and to generate an internal clock signal synchronized to the external clock signal; 
 a buffer adapted to buffer the internal clock signal and to output differential reference clock signals; and 
 a duty cycle correction circuit adapted to generate first control signals having desired offsets corresponding to differences in duty cycles of the differential reference clock signals, and to output the first control signals to the DLL core under the control of a switching control signal, 
 wherein the DLL core corrects a duty cycle of the internal clock signal in response to the first control signals, 
 wherein in a duty-cycle error analysis mode, the switching control signal selectively turns on and turns off the duty cycle correction circuit to inhibit output of the first control signals to the DLL core, and 
 wherein the duty cycle correction circuit is adapted to receive complementary transmission circuit control signals, and includes first and second storage units adapted, in response to the complementary transmission circuit control signals being activated, to store voltages generated by the differential reference clock signals, and wherein the switching control signal selectively inhibits output of the first control signals to the DLL core while the complementary transmission circuit control signals are activated to store voltages generated by the differential reference clock signals in the first and second storage units. 
 
     
     
       5. The delay locked loop of  claim 4 ,
 wherein the switching control signal selectively turns off an output of the duty cycle correction circuit to inhibit output of the first control signals to the DLL core while at a same time the duty cycle correction circuit continues to generate the first control signals having the desired offsets corresponding to differences in duty cycles of the differential reference clock signals. 
 
     
     
       6. The delay locked loop of  claim 4 , wherein the delay locked loop further comprises a pad adapted to receive the switching control signal. 
     
     
       7. The delay locked loop of  claim 4 , wherein the delay locked loop further comprises a mode register set for generating the switching control signal. 
     
     
       8. The delay locked loop of  claim 4 , wherein the buffer comprises a plurality of serially interconnected inverters adapted to generate the differential reference clock signals. 
     
     
       9. The delay locked loop of  claim 8 , wherein each of the plurality of inverters includes one PMOS transistor and one NMOS transistor, which are connected serially. 
     
     
       10. A delay locked loop (DLL) comprising:
 a DLL core adapted to receive an external clock signal and to generate an internal clock signal synchronized to the external clock signal; 
 a buffer adapted to buffer the internal clock signal and to output differential reference clock signals; and 
 a duty cycle correction circuit adapted to generate first control signals having desired offsets corresponding to differences in duty cycles of the differential reference clock signals, and to output the first control signals to the DLL core under the control of a switching control signal, 
 wherein the DLL core corrects a duty cycle of the internal clock signal in response to the first control signals, 
 wherein in a duty-cycle error analysis mode, the switching control signal selectively turns on and turns off the duty cycle correction circuit to inhibit output of the first control signals to the DLL core, 
 wherein the duty cycle correction circuit includes:
 first and second outputs for outputting the first control signals; 
 first and second storage units; 
 a transmission circuit adapted to receive complementary transmission circuit control signals, and in response to complementary transmission circuit control signals being activated, to store voltages generated by the differential reference clock signals in the first and second storage units; and 
 a switching circuit adapted, in response to the switching control signal, to selectively connect the stored voltages of the first and second storage units to the first and second outputs as the first control signals, and 
 
 wherein the switching circuit responds to the switching control signal to disconnect the stored voltages of first and second storage units from the first and second outputs while the complementary transmission circuit control signals are activated to store the voltages generated by the differential reference clock signals in the first and second storage units. 
 
     
     
       11. A delay locked loop (DLL) circuit comprising:
 a DLL core configured to receive an external clock signal and generate an internal clock signal synchronized to the external clock signal; and,   a buffer connected to said DLL core configured to buffer the internal clock signal and generate a clock output signal and a complementary clock output signal; and,   a duty cycle correction circuit connected to said buffer configured to receive the clock output signal and complementary clock output signal generated by said buffer and to provide to said DLL core a duty cycle correction output, and a complementary duty cycle correction output comprising;   a first transmission circuit connected between the first differential output terminal of the differential amplifier and a first node, and adapted to transmit to the first node a first one of the amplified differential reference clock signals appearing at the first differential output terminal of the differential amplifier;   a second transmission circuit connected between the second differential output terminal of the differential amplifier and a second node, and adapted to transmit to the second node a second one of the amplified differential reference clock signals appearing at the second differential output terminal of the differential amplifier;   a differential amplifier having inputs configured to receive the clock output signal and the complementary clock output signal from said buffer; and,   a first storage unit connected to a first output of said differential amplifier, connected to the duty cycle correction output, and configured to store a first charge corresponding to the duty cycle of the internal clock signal, and,   a second storage unit connected to the second output of said differential amplifier, connected to the complementary duty cycle correction output, and configured to store a second charge corresponding to the duty cycle of the internal clock signal, and,   an equalize circuit connected between the first output and the second output of said differential amplifier having an input to receive a reset signal, wherein said duty cycle correction circuit provides a differential signal on the duty cycle output and the complementary duty cycle output based the duty cycle of the internal clock signal clock signal when the reset signal is deactivated, and provides an equalized signal on the first and second outputs when the reset signal is activated;   a switching circuit connected between the first node and a first input terminal of the DLL core, and connected between the second node and a second input terminal of the DLL core, the switching circuit having a control terminal adapted to receive the switching control signal to selectively provide the signals of the first and second nodes to the first and second input terminals of the DLL core as the first control signals, and wherein the first transmission circuit is adapted to provide the first one of the amplified differential reference clock signals to the first node, and the second transmission circuit is adapted to provide the second one of the amplified differential reference clock signals to the second node, while the switching control signal has an activated state and while the switching control signal has a deactivated state.    
     
     
       12. A delay locked loop (DLL) circuit as in claim 11, wherein said equalize circuit includes a transistor with a gate connected to the reset signal.  
     
     
       13. A delay locked loop (DLL) circuit as in claim 12, wherein said transistor is a PMOS transistor and the reset signal has a high level when deactivated and a low level when activated.  
     
     
       14. A delay locked loop (DLL) circuit as in claim 11, wherein said first storage unit and second storage unit are both MOS transistors.  
     
     
       15. A delay locked loop (DLL) circuit as in claim 14, wherein said first storage unit is a NMOS transistor having a gate connected to the first output of said differential amplifier and the source/drain connected to a supply voltage, and said second storage unit is a NMOS transistor having a gate connected to the second outputs of said differential amplifier and the source/drain connected to a supply voltage.  
     
     
       16. A delay locked loop (DLL) circuit as in claim 11, wherein the duty cycle is corrected to a 50% duty cycle.  
     
     
       17. A delay locked loop (DLL) circuit as in claim 11, wherein the equalize circuit is directly connected between the first output and the second output of said differential amplifier.  
     
     
       18. A delay locked loop (DLL) circuit as in claim 11, wherein the first storage unit is connected to the first output of the differential amplifier through a first transmission gate and the second storage unit is connected to the second output of the differential amplifier through a second transmission gate.  
     
     
       19. A delay locked loop (DLL) circuit as in claim 11, wherein the first storage unit is connected to the duty cycle correction output through a first transmission gate and the second storage unit is connected to the complementary duty cycle correction output through a second transmission gate.  
     
     
       20. A delay locked loop (DLL) circuit as in claim 19, wherein the first transmission gate and the second transmission gate are controlled by a pad.  
     
     
       21. A delay locked loop (DLL) circuit as in claim 19, wherein the first transmission gate and the second transmission gate are controlled by a mode register.  
     
     
       22. A delay locked loop (DLL) circuit as in claim 11, wherein the equalized signal has a voltage level between the voltage levels of the duty cycle correction output and the complementary duty cycle correction output when the reset signal is deactivated.  
     
     
       23. A method for correcting duty cycle error in a delay locked loop (DLL) circuit that includes a DLL core configured to receive an external clock signal and generate an internal clock signal synchronized to the external clock signal and a buffer connected to said DLL core configured to buffer the internal clock signal and generate a clock output signal and a complementary clock output signal comprising the steps of:
 amplifying the clock output signal and the complementary clock output signal to allow processing, and,   integrating the clock output signal to produce a duty cycle correction signal indicating the duty cycle of the internal clock signal, and,   integrating the complimentary clock output signal to produce a complementary duty cycle correction signal indicating the duty cycle of the internal clock signal,   equalizing the duty cycle correction signal the complementary duty cycle correction signal when a reset signal is activated and inhibiting equalization of the duty cycle correction signal the complementary duty cycle correction signal when a reset signal is deactivated, and,   sending the duty cycle correction signal and the complementary duty cycle correction signal to the DLL core to correct the duty cycle of the internal clock signal when the reset signal is deactivated and to not correct the duty cycle of the internal clock signal when the reset signal is activated.    
     
     
       24. A method for correcting duty cycle errors in a delay locked loop (DLL) as in claim 23, wherein the duty cycle is corrected to a 50% duty cycle.  
     
     
       25. A method for correcting duty cycle errors in a delay locked loop (DLL) as in claim 23, wherein the reset signal is activated when there is no duty cycle error.  
     
     
       26. A method for correcting duty cycle errors in a delay locked loop (DLL) as in claim 23, wherein the reset signal is provided by a mode register.  
     
     
       27. A method for correcting duty cycle errors in a delay locked loop (DLL) as in claim 23, wherein the reset signal is provided by a pad.  
     
     
       28. A method for correcting duty cycle errors in a delay locked loop (DLL) as in claim 23, wherein two fixed voltage signals are sent to the DLL core when the reset signal is activated.  
     
     
       29. A method for correcting duty cycle errors in a delay locked loop (DLL) as in claim 23, wherein two ground signals are sent to the DLL core when a switching control signal is activated.  
     
     
       30. A system for providing complementary clock signals from an external clock signal comprising:
 a DLL core configured to receive an external clock signal and generate an internal clock signal synchronized to the external clock signal; and,   a buffer connected to said DLL core configured to buffer the internal clock signal and generate a clock output signal and a complementary clock output signal; and,   a duty cycle correction circuit connected to said buffer configured to receive the clock output signal and complementary clock output signal generated by said buffer and to provide to said DLL core a duty cycle correction output, and a complementary duty cycle correction output comprising;   a first transmission circuit connected between the first differential output terminal of the differential amplifier and a first node, and adapted to transmit to the first node a first one of the amplified differential reference clock signals appearing at the first differential output terminal of the differential amplifier;   a second transmission circuit connected between the second differential output terminal of the differential amplifier and a second node, and adapted to transmit to the second node a second one of the amplified differential reference clock signals appearing at the second differential output terminal of the differential amplifier;   a differential amplifier having inputs configured to receive the clock output signal and the complementary clock output signal from said buffer; and,   a first storage unit connected to a first output of said differential amplifier connected to the duty cycle correction output, and configured to store a first charge corresponding to the duty cycle of the internal clock signal, and,   a second storage unit connected to the second output of said differential amplifier, connected to the complementary duty cycle correction output, and configured to store a second charge corresponding to the duty cycle of the internal clock signal, and,   an equalize circuit connected between the first output and the second output of said differential amplifier having an input to receive a reset signal, wherein said duty cycle correction circuit provides a differential signal on the duty cycle output and the complementary duty cycle output based the duty cycle of the internal clock signal clock signal when the reset signal is deactivated, and provides an equalized signal on the first and second outputs when the reset signal is activated,   a switching circuit connected between the first node and a first input terminal of the DLL core, and connected between the second node and a second input terminal of the DLL core, the switching circuit having a control terminal adapted to receive the switching control signal to selectively provide the signals of the first and second nodes to the first and second input terminals of the DLL core as the first control signals, and wherein the first transmission circuit is adapted to provide the first one of the amplified differential reference clock signals to the first node, and the second transmission circuit is adapted to provide the second one of the amplified differential reference clock signals to the second node, while the switching control signal has an activated state and while the switching control signal has a deactivated state.    
     
     
       31. A system for providing complementary clock signals as in claim 30, wherein said equalize circuit includes a transistor with a gate connected to the reset signal.  
     
     
       32. A system for providing complementary clock signals as in claim 31, wherein said transistor is a PMOS transistor and the reset signal has a high level when deactivated and a low level when activated.  
     
     
       33. A system for providing complementary clock signals as in claim 30, wherein said first storage unit and second storage unit are both MOS transistors.  
     
     
       34. A system for providing complementary clock signals as in claim 33, wherein said first storage unit is a NMOS transistor having a gate connected to the first output of said differential amplifier and the source/drain connected to a supply voltage, and said second storage unit is a NMOS transistor having a gate connected to the second outputs of said differential amplifier and the source/drain connected to a supply voltage.  
     
     
       35. A system for providing complementary clock signals as in claim 30, wherein the clock output signal and complementary clock output signal are corrected to a substantially 50% duty cycle.  
     
     
       36. A system for providing complementary clock signals as in claim 30, wherein the equalize circuit is directly connected between the first output and the second output of said differential amplifier.  
     
     
       37. A system for providing complementary clock signals as in claim 30, wherein the first storage unit is connected to the first output of the differential amplifier through a first transmission gate and the second storage unit is connected to the second output of the differential amplifier through a second transmission gate.  
     
     
       38. A system for providing complementary clock signals as in claim 30, wherein the first storage unit is connected to the duty cycle correction output through a first transmission gate and the second storage unit is connected to the complementary duty cycle correction output through a second transmission gate.  
     
     
       39. A system for providing complementary clock signals as in claim 38, wherein the first transmission gate and the second transmission gate are controlled by a pad.  
     
     
       40. A system for providing complementary clock signals as in claim 38, wherein the first transmission gate and the second transmission gate are controlled by a mode register.  
     
     
       41. A system for providing complementary clock signals as in claim 30, wherein the equalized signal has a voltage level between the voltage levels of the duty cycle correction output and the complementary duty cycle correction output when the reset signal is deactivated.