Non-volatile semiconductor storage device

Abstract

A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.

What is claimed is: 
     
       1. A non-volatile semiconductor storage device comprising:
 a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and 
 a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells; 
 each of the plurality of transfer transistors comprising: 
 a gate electrode formed on a semiconductor substrate via a gate insulation film; 
 diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers; and 
 upper layer wirings provided above the diffusion layers, 
 wherein 
 the transfer transistors comprise enhancement-type transistors and depression-type transistors, 
 the upper layer wirings provided above the transfer transistors corresponding to the enhancement-type transistors are provided with a predetermined voltage at least when the transfer transistors become conductive to prevent depletion of the diffusion layer, and 
 the upper layer wirings provided above the transfer transistors corresponding to the depression-type transistors are supplied with a fixed voltage smaller than a voltage applied to their gates. 
 
     
     
       2. The non-volatile semiconductor storage device according to  claim 1 , further comprising:
 a row decoder selecting a word line provided above the memory cell array, 
 wherein the transfer transistors are included in the row decoder. 
 
     
     
       3. The non-volatile semiconductor storage device according to  claim 1 , wherein
 the upper layer wirings of the transfer transistors corresponding to the enhancement-type transistors are provided with the same voltage as that of the gate electrode. 
 
     
     
       4. The non-volatile semiconductor storage device according to  claim 3 , wherein
 the upper layer wirings of the transfer transistors corresponding to the enhancement-type transistors are short-circuited to the gate electrode. 
 
     
     
       5. The non-volatile semiconductor storage device according to  claim 1 , wherein
 the upper layer wirings of the transfer transistors corresponding to the enhancement-type transistors are provided with the same voltage as that of the diffusion layers. 
 
     
     
       6. The non-volatile semiconductor storage device according to  claim 5 , wherein
 the upper layer wirings of the transfer transistors corresponding to the enhancement-type transistors are short-circuited to the diffusion layers. 
 
     
     
       7. The non-volatile semiconductor storage device according to  claim 1 , further comprising:
 a short-circuit wiring short-circuiting the upper layer wirings to the gate electrode. 
 
     
     
       8. The non-volatile semiconductor storage device according to  claim 1 , wherein
 the memory cell array comprises NAND cells including a plurality of serially-connected memory cells, and selection transistors connected to the NAND cells. 
 
     
     
       9. The non-volatile semiconductor storage device according to  claim 1 , wherein
 each of the diffusion layers comprises a high concentration area with a first impurity concentration and an LDD area with a second impurity concentration lower than the first impurity concentration. 
 
     
     
       10. The non-volatile semiconductor storage device according to  claim 9 , wherein
 the upper layer wirings are provided above the LDD areas. 
 
     
     
       11. The non-volatile semiconductor storage device according to  claim 1 , wherein
 the plurality of transfer transistors share the gate electrode as well as the upper layer wirings that are disposed in a continuous manner. 
 
     
     
       12. The non-volatile semiconductor storage device according to  claim 1 , wherein
 the plurality of transfer transistors share the gate electrode, and 
 the upper layer wirings are separately disposed for one or two of the plurality of transfer transistors. 
 
     
     
       13. The non-volatile semiconductor storage device according to  claim 1 , further comprising:
 a signal line electrically connected to the diffusion layers, wherein the upper layer wirings are short-circuited to the signal line. 
 
     
     
       14. A non-volatile semiconductor storage device comprising:
 a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and 
 a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells; 
 each of the plurality of transfer transistors comprising: 
 a gate electrode formed on a semiconductor substrate via a gate insulation film; 
 diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers; and 
 upper layer wirings provided above the diffusion layers, 
 wherein 
 the transfer transistors comprise enhancement-type transistors and depression-type transistors, 
 the upper layer wirings provided above the transfer transistors corresponding to the enhancement-type transistors are provided with the same voltage as applied to the diffusion layers or the gate voltage at least when the transfer transistors become conductive, and 
 the upper layer wirings provided above the transfer transistors corresponding to the depression-type transistors are supplied with a fixed voltage smaller than a voltage applied to their gates. 
 
     
     
       15. The non-volatile semiconductor storage device according to  claim 14 , further comprising:
 a row decoder selecting a word line provided above the memory cell array, 
 wherein the transfer transistors are included in the row decoder. 
 
     
     
       16. The non-volatile semiconductor storage device according to  claim 14 , wherein
 the upper layer wirings of the transfer transistors corresponding to the enhancement-type transistors are short-circuited to the gate electrode. 
 
     
     
       17. The non-volatile semiconductor storage device according to  claim 14 , wherein
 the upper layer wirings of the transfer transistors corresponding to the enhancement-type transistors are short-circuited to the diffusion layers. 
 
     
     
       18. A non-volatile semiconductor storage device comprising:
 a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and 
 a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells; 
 each of the plurality of transfer transistors comprising: 
 a gate electrode formed on a semiconductor substrate via a gate insulation film; 
 diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers; and 
 upper layer wirings provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive, 
 wherein the plurality of transfer transistors share the gate electrode, and 
 the upper layer wirings are separately disposed for one or two of the plurality of transfer transistors. 
 
     
     
       19. A non-volatile semiconductor storage device comprising:
 a memory cell array including a plurality of memory cells, the memory cells storing data in a non-volatile manner;   a plurality of transfer transistors configured to transfer a voltage to the memory cells, each of the plurality of transfer transistors including a gate electrode formed on a semiconductor substrate via a gate insulation film and drain/source regions formed to sandwich the gate electrode therebetween; and   first wirings connected to the drain/source regions of the plurality of transfer transistors via contacts respectively, each of the first wirings including a first line provided above one of the drain/source regions; and   upper layer wirings provided above the drain/source regions of the plurality of transfer transistors, each of the upper layer wirings including a plurality of second lines located near the gate electrode as compared to the first line above the one of the drain/source regions, the plurality of second lines extending parallel with each other,   wherein the plurality of transfer transistors share the gate electrode, and the upper layer wirings are separately disposed for one or two of the plurality of transfer transistors.    
     
     
       20. The non-volatile semiconductor storage device according to claim 19, further comprising a row decoder selecting a word line provided above the memory cell array, wherein the transfer transistors are included in the row decoder.  
     
     
       21. The non-volatile semiconductor storage device according to claim 19, wherein both the first line and the plurality of second lines extend in the first direction.  
     
     
       22. The non-volatile semiconductor storage device according to claim 19, further comprising second wirings connected to the drain/source regions of the plurality of transfer transistors via contacts respectively, each of the second wirings including a third line provided above the other of the drain/source regions; and
 wherein a plurality of fourth lines are provided near the gate electrode as compared to the third line above the other of the drain/source regions, the plurality of fourth lines extending parallel with each other.    
     
     
       23. The non-volatile semiconductor storage device according to claim 22, further comprising a row decoder selecting a word line provided above the memory cell array, wherein the transfer transistors are included in the row decoder.  
     
     
       24. The non-volatile semiconductor storage device according to claim 19, wherein both the first line and the plurality of second lines are arranged in a same layer.  
     
     
       25. The non-volatile semiconductor storage device according to claim 22, wherein the first line, the plurality of second lines, the third line, and the plurality of fourth lines are arranged in a same layer.  
     
     
       26. The non-volatile semiconductor storage device according to claim 19, wherein the plurality of second lines are connected to the first line.  
     
     
       27. The non-volatile semiconductor storage device according to claim 19, wherein the plurality of second lines are arranged in a same layer as lead wirings of control gates of the plurality of memory cells.  
     
     
       28. The non-volatile semiconductor storage device according to claim 19, wherein the upper layer wirings are separately disposed for one of the plurality of transfer transistors.  
     
     
       29. The non-volatile semiconductor storage device according to claim 22, wherein the plurality of fourth lines are connected to the third line.  
     
     
       30. A non-volatile semiconductor storage device comprising:
 a memory cell array including a plurality of memory cells, the memory cells storing data in a non-volatile manner;   a plurality of transfer transistors configured to transfer a voltage to the memory cells, each of the plurality of transfer transistors including a gate electrode formed on a semiconductor substrate via a gate insulation film and drain/source regions formed to sandwich the gate electrode therebetween; and   wirings provided above the drain/source regions of the plurality of transfer transistors, each of the wirings including a first portion and a second portion both provided above one of the drain/source regions, the first portion being connected to the one of the drain/source regions via a contact and the second portion being arranged between the first portion and the gate electrode,   wherein the plurality of transfer transistors share the gate electrode, and   the wirings are separately disposed for one or two of the plurality of transfer transistors.    
     
     
       31. The non-volatile semiconductor storage device according to claim 30, wherein the second portion is not connected to the one of the drain/source regions directly via a contact.  
     
     
       32. The non-volatile semiconductor storage device according to claim 30, further comprising a row decoder selecting a word line provided above the memory cell array, wherein the transfer transistors are included in the row decoder.  
     
     
       33. The non-volatile semiconductor storage device according to claim 30, wherein both the first portion and the second portion extend in a first direction.  
     
     
       34. The non-volatile semiconductor storage device according to claim 30, wherein both the first portion and the second portion are arranged in a same layer.  
     
     
       35. A non-volatile semiconductor storage device comprising:
 a memory cell array including a plurality of memory cells, the memory cells storing data in a non-volatile manner;   a plurality of transfer transistors configured to transfer a voltage to the memory cells, each of the plurality of transfer transistors including a gate electrode formed on a semiconductor substrate via a gate insulation film and drain/source regions formed to sandwich the gate electrode therebetween; and   wirings provided above the drain/source regions of the plurality of transfer transistors, each of the wirings including a first portion and a second portion both provided above one of the drain/source regions, the first portion being connected to the one of the drain/source regions via a contact and the second portion being led from the first portion and extending toward a gate electrode side above the one of the drain/source regions,   wherein the plurality of transfer transistors share the gate electrode, and   the wirings are separately disposed for one or two of the plurality of transfer transistors.    
     
     
       36. The non-volatile semiconductor storage device according to claim 35, wherein the second portion is not connected to the one of the drain/source regions directly via a contact.  
     
     
       37. The non-volatile semiconductor storage device according to claim 35, further comprising a row decoder selecting a word line provided above the memory cell array, wherein the transfer transistors are included in the row decoder.  
     
     
       38. The non-volatile semiconductor storage device according to claim 35, wherein both the first portion and the second portion are arranged in a same layer.