Configurable voltage controlled oscillator system and method including dividing forming a portion of two or more divider paths

Abstract

A phase lock loop with multiple divider paths is presented herein. The phase lock loop can be used to provide a wide range of frequencies. The phase lock loop can also be used as a portion of a clock multiplier unit or a clock data and recovery unit.

The invention claimed is: 
     
       1. A method for providing output signals with a plurality of frequencies, said method comprising:
 comparing phases between an input signal and a feedback signal; 
 generating a frequency signal, wherein the frequency signal is dependent on the a difference between the a phase of the input signal and the a phase of the feedback signal; and 
 dividing the a frequency of the frequency signal by a plurality of divider paths, wherein at least one divider forms a portion of at least two of the plurality of divider paths, 
 wherein the at least one divider that forms the portion of the at least two of the plurality of divider paths is directly coupled to a next divider in at least one of the plurality of divider paths, and wherein each of the at least two of the plurality of divider paths after the at least one divider includes a plurality of dividers. 
 
     
     
       2. The method of  claim 1 , further comprising outputting a plurality of output frequency signals. 
     
     
       3. The method of  claim 2 , wherein the plurality of output frequency signals further comprise an OC-3 signal, an OC-12 signal, an OC-48 signal, and a Gigabit Ethernet signal. 
     
     
       4. The method of claim 2, further comprising deriving the plurality of output frequency signals from an output signal of a phase lock loop.  
     
     
       5. The method of claim 2, further comprising providing a first one of the plurality of output frequency signals to a transmitter or a receiver.  
     
     
       6. The method of claim 2, further comprising providing a first one of the plurality of output frequency signals to a transmitter to transmit data.  
     
     
       7. The method of claim 6, wherein the first one of the plurality of output frequency signals is a high frequency clock signal.  
     
     
       8. The method of claim 6, wherein the first one of the plurality of output frequency signals is a signal with a frequency on the order of 10 8  Hz.  
     
     
       9. The method of claim 6, wherein the data is transmitted at one of a plurality of different data rates.  
     
     
       10. The method of claim 6, wherein the data is transmitted with one of a plurality of different formats.  
     
     
       11. The method of claim 2, further comprising providing a first one of the plurality of output frequency signals to a receiver to receive data.  
     
     
       12. The method of claim 11, wherein the first one of the plurality of output frequency signals is a high frequency signal.  
     
     
       13. The method of claim 11, wherein the first one of the plurality of output frequency signals is a signal with a frequency on the order of 10 8  Hz.  
     
     
       14. The method of claim 11, wherein the data is received at one of a plurality of different possible data rates.  
     
     
       15. The method of claim 11, wherein the data is received in one of a plurality of different possible formats.  
     
     
       16. The method of claim 1, wherein the comparing phases includes comparing phases in a phase detector, the method further comprising:
 providing a first output signal from a first divider path of the plurality of divider paths as a second feedback signal to the phase detector, and   providing a second output signal from a second divider path of the plurality of divider paths as a second frequency signal to a transmitter.    
     
     
       17. The method of claim 16, further comprising:
 controlling the frequency of the feedback signal using a control signal.    
     
     
       18. The method of claim 1, further comprising:
 comparing the phases in a phase detector,   providing a first output signal from a first divider path of the plurality of divider paths as a second feedback signal to the phase detector, and   providing a second output signal from a second divider path of the plurality of divider paths to a receiver.    
     
     
       19. The method of claim 18, further comprising:
 controlling the frequency of the feedback signal using a control signal.    
     
     
       20. The method of claim 1, wherein the generating is performed by a plurality of voltage controlled oscillators (VCOs), each of which provides a respective VCO signal.  
     
     
       21. The method of claim 20, wherein the generating comprises selecting one of the plurality of VCO signals with a multiplexer.  
     
     
       22. The method of claim 1, further comprising:
 generating a plurality of output signals for a transmitter; and   selecting, with a multiplexer, one of the plurality of output signals to be provided to the transmitter.    
     
     
       23. The method of claim 1, wherein the comparing phases includes comparing phases in a phase detector, the method further comprising:
 providing a first output signal from a first divider path of the plurality of divider paths as a second feedback signal to the phase detector,   providing a second output signal from a second divider path of the plurality of divider paths as a second frequency signal to a transmitter, and   using the second frequency signal for transmitting data,   wherein the transmitting data includes transmitting with one of a plurality of data rates.    
     
     
       24. A method for providing output signals with a plurality of frequencies, said method comprising:
 comparing phases between an input signal and a feedback signal;   generating a frequency signal, wherein the frequency signal is dependent on a difference between a phase of the input signal and a phase of the feedback signal; and   dividing a frequency of the frequency signal by a plurality of divider paths, wherein at least one divider forms a portion of at least two of the plurality of divider paths,   wherein the dividing further comprises, after the dividing in the at least one divider that forms the portion of the at least two of the plurality of divider paths, providing a signal to the at least one divider, then to a multiplexer and then to a series of dividers.    
     
     
       25. The method of claim 24, further comprising outputting a plurality of output frequency signals.  
     
     
       26. The method of claim 25, further comprising deriving the plurality of output frequency signals from an output signal of a phase lock loop.  
     
     
       27. The method of claim 25, further comprising providing a first one of the plurality of output frequency signals to a transmitter or a receiver.  
     
     
       28. The method of claim 24, wherein the generating is performed by a plurality of voltage controlled oscillators (VCOs), each of which provides a respective VCO signal.  
     
     
       29. A method for providing output signals with a plurality of frequencies, said method comprising:
 comparing phases between an input signal and a feedback signal;   generating a frequency signal, wherein the frequency signal is dependent on a difference between a phase of the input signal and a phase of the feedback signal;   dividing a frequency of the frequency signal by a plurality of divider paths, wherein at least one divider forms a portion of at least two of the plurality of divider paths;   providing a signal divided by the at least one divider to a multiplexer; and   providing a signal output by the multiplexer to an additional divider.