Memory module and memory system

Abstract

In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.

What is claimed is: 
     
       1. A method comprising:
 performing a first transfer of first data, the first transfer being performed via through electrodes extending through a plurality of memory chips stacked on a control IO chip and connecting electrically between the control IO chip and each of the memory chips; and
 performing a second transfer of second data, the second transfer being performed via data lines connecting electrically between a controller and the control IO chip, and a bus width of the through electrodes being broader than that of the data lines. 
 
 
     
     
       2. The method as claimed in  claim 1 , wherein the first transfer of the first data is performed in parallel via through electrodes between the control IO chip and each of the memory chips and the second transfer of the second data is performed in serial via data lines between the controller and the control IO chip. 
     
     
       3. The method as claimed in  claim 1 , wherein the bus width of the through electrodes is 2n (n denotes a natural number of 1 or more) times of that of the data lines. 
     
     
       4. The method as claimed in  claim 1 , further comprising:
 generating the first data from a plurality of the second data, the first data comprising a first number of bits, each of the second data comprising a second number of bits, and the first number of the first data being larger than the second number of the second data. 
 
     
     
       5. The method as claimed in  claim 4 , wherein a sum of total bits configuring the plurality of the second data is equal to the first number of the first data. 
     
     
       6. The method as claimed in  claim 1 , further comprising:
 generating a plurality of the second data from the first data, the first data comprising a first number of bits, each of the second data comprising a second number of bits, and the first number of the first data being larger than the second number of the second data. 
 
     
     
       7. The method as claimed in  claim 6 , wherein a sum of total bits configuring the plurality of the second data is equal to the first number of the first data. 
     
     
       8. A method comprising:
 supplying a plurality of external data to data terminals of a control IO chip in serial to each other; 
 making up internal data in response to the supplied external data, the internal data comprising a first number of bits, each of the supplied external data comprising a second number of bits, and the first number being larger than the second number; and 
 writing bits of the made-up internal data into selected one among a plurality of memory chips in parallel to each other, the memory chips being stacked on the control IO chip, the writing being performed via thorough electrodes extending through the memory chips and connecting electrically between the control IO chip and each of the memory chips. 
 
     
     
       9. The method as claimed in  claim 8 , wherein the first number is 2n (n denotes a natural number of 1 or more) times of the second number. 
     
     
       10. The method as claimed in  claim 8 , wherein a sum of total bits configuring the plurality of the second data is equal to the first number of the first data. 
     
     
       11. The method as claimed in  claim 8 , wherein the through electrodes has a broader bus width than the data terminals of the control IO chip. 
     
     
       12. The method as claimed in  claim 8 , further comprising;
 supplying address information to address terminals of a control IO chip, the address information being transferred via the through electrodes that is different from one that transfer the internal data; and 
 selecting, in response to a content of the supplied address information, the selected one among the memory chips. 
 
     
     
       13. A method comprising:
 reading out bits of internal data from selected one among a plurality of memory chips in parallel to each other, the memory chips being stacked on a control IO chip, the read being performed via thorough electrodes extending through the memory chips and connecting electrically between the control IO chip and each of the memory chips, 
 making up a plurality of external data in response to the read-out internal data, the internal data comprising a first number of the bits, each of the external data comprising a second number of bits, and the first number being larger than the second number; and 
 sending bits of the made-up external data via data terminals of the IO chip to external in serial to each other. 
 
     
     
       14. The method as claimed in  claim 13 , wherein the first number is 2n (n denotes a natural number of 1 or more) times of the second number. 
     
     
       15. The method as claimed in  claim 13 , wherein a sum of total bits configuring the plurality of the second data is equal to the first number of the first data. 
     
     
       16. The method as claimed in  claim 13 , wherein the through electrodes has a broader bus width than the data terminals of the control IO chip. 
     
     
       17. The method as claimed in  claim 13 , further comprising:
 supplying address information to a control IO chip, the address information being transferred via the through electrodes that is different from one that transfer the internal data; and 
 selecting, in response to a content of the supplied address information, selected one among the memory chips. 
 
     
     
       18. A method comprising:
 making an access to a semiconductor device that comprises a first semiconductor chip and a second semiconductor chip, the second semiconductor chip being stacked over the first semiconductor chip; 
 accepting the access at the first semiconductor chip to perform a data transfer between the first semiconductor chip and an outside of the semiconductor device in a unit of a first number of bits; and 
 performing, in response to the accepting, a data transfer between the first and second semiconductor chips in a unit of a second number of bits, the second number being greater than the first number. 
 
     
     
       19. The method as claimed in  claim 18 , wherein the semiconductor device further comprising a third semiconductor chip stacked over the second semiconductor chip, and the performing is carried out between the first semiconductor chip and at least one of the second and third semiconductor chips. 
     
     
       20. The method as claimed in  claim 19 , wherein the second semiconductor chip including a plurality of first through electrodes each penetrating the second semiconductor chip and the third semiconductor chip including a plurality of second through electrodes each penetrating the third semiconductor chip, each of the first through electrodes being connected to an associated one of the second through electrodes, the data transfer between the first semiconductor chip and the at least one of the second and third semiconductor chips being performed through at least one of the first and second through electrodes. 
     
     
       21. The method as claimed in  claim 20 , wherein a bus width of the first through electrodes is equal to that of second through electrodes. 
     
     
       22. The method as claimed in  claim 19 , further comprising:
 selecting one of the second and the third semiconductor chip to carry out the performing between the first semiconductor chip and the one of the second and third semiconductor chips, and 
 carrying out the performing between the first semiconductor chip and the selected one of the second and third semiconductor chips in parallel to each other. 
 
     
     
       23. A memory module comprising:
 a plurality of stacked memory chips;   a serial presence detect chip stacked with the plurality of memory chips, wherein the serial presence detect chip is stacked over the plurality of stacked memory chips; and   a plurality of through electrodes connecting each of the plurality of stacked memory chips and the serial presence detect chip.   
     
     
       24. The memory module of claim 23 further comprising an IO chip stacked with the plurality of stacked memory chips and the serial presence detect chip and connected to the plurality of through electrodes. 
     
     
       25. The memory module of claim 24 wherein the plurality of stacked memory chips are stacked over the IO chip. 
     
     
       26. The memory module of claim 23 wherein the serial presence detect chip determines an operation condition of the plurality of stacked memory chips. 
     
     
       27. The memory module of claim 23 wherein the serial presence detect chip comprises memory. 
     
     
       28. The memory module of claim 27 wherein the serial presence detect chip comprises ROM. 
     
     
       29. The memory module of claim 23 wherein the serial presence detect chip comprises an indication of a selected one of memory capacity, bank constitution, and assured operation speed information for the plurality of stacked memory chips. 
     
     
       30. The memory module of claim 23 wherein the serial presence detect chip provides information to set control conditions at system boot time.