USRE45931EExpiredUtility

Method of manufacturing a semiconductor device

58
Assignee: RENESAS ELECTRONICS CORPPriority: Nov 29, 1999Filed: May 30, 2014Granted: Mar 15, 2016
Est. expiryNov 29, 2019(expired)· nominal 20-yr term from priority
Inventors:Tsutomu WadaMasachika Masuda
H10W 72/5522H10W 74/00H10W 72/0198H10W 72/884H10W 90/754H10W 46/607H10W 46/601H10W 46/103H10W 72/07533H10W 72/07532H10W 90/734H10W 74/117H10W 74/016H10W 99/00H10W 74/014H10W 72/5525H10D 64/011H01L 21/44H01L 2924/01079
58
PatentIndex Score
0
Cited by
53
References
37
Claims

Abstract

For the manufacturing of semiconductor devices, in which multiple semiconductor chips which are mounted on a wiring substrate are processed for block molding and thereafter the wiring substrate is diced into individual resin-molded semiconductor devices, disclosed herein is a technique for easily determining the position of each resin-molded semiconductor device in its former state on the wiring substrate even after the dicing process. The processing steps include implementing the block molding with resin for multiple semiconductor chips mounted on a wiring substrate and thereafter dicing the wiring substrate into individual resin-molded semiconductor devices, with the substrate dicing step being preceded by a step of appending an address information pattern to each of the resin-molded semiconductor devices.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A method of manufacturing a semiconductor device including processing steps of implementing the block molding with resin for a plurality of semiconductor chips which are mounted on a wiring substrate and thereafter dicing the wiring substrate into a plurality of resin-molded semiconductor devices,
 wherein said method further includes a step, which precedes said substrate dicing step, of appending address information to each of the resin-molded semiconductor devices.   
     
     
       2. A method of manufacturing a semiconductor device according to  claim 1  including processing steps of implementing the block molding with resin for a plurality of semiconductor chips which are mounted on a wiring substrate and thereafter dicing the wiring substrate into a plurality of resin-molded semiconductor devices,
 wherein said method further includes a step, which precedes said substrate dicing step, of appending address information to each of the resin-molded semiconductor devices, and  
 wherein said address information includes information indicative of the position of each of the resin-molded semiconductor devices within the wiring substrate. 
 
     
     
       3. A method of manufacturing a semiconductor device including processing steps of implementing the block molding with resin for a plurality of semiconductor chips which are mounted on a wiring substrate and thereafter dicing the wiring substrate into a plurality of resin-molded semiconductor devices,
 wherein said method further includes a step, which precedes said substrate dicing step, of appending address information of each of the resin-molded semiconductor devices to part of the wiring substrate. 
 
     
     
       4. A method of manufacturing a semiconductor device according to  claim 3 , wherein further including a step of forming wire patterns with a wiring material on the wiring substrate and shaping said wiring material such that said address information is shaped in a the wiring material which has been formed in a the step of forming wire patterns on the wiring substrate. 
     
     
       5. A method of manufacturing a semiconductor device according to  claim 4 , wherein said address information also has the role of index information which orients the resin-molded semiconductor device on a circuit board at packaging. 
     
     
       6. A method of manufacturing a semiconductor device according to  claim 4 , wherein said address information is shaped at a position different from the position of index information which orients the resin-molded semiconductor device on a circuit board at packaging. 
     
     
       7. A method of manufacturing a semiconductor device including processing steps of implementing the block molding with resin for a plurality of semiconductor chips which are mounted on a wiring substrate and thereafter dicing the wiring substrate into a plurality of resin-molded semiconductor devices,
 wherein said method further includes a step, which precedes said substrate dicing step that follows the block molding with resin of said semiconductor chips, of appending address information to each of the resin-molded semiconductor devices.   
     
     
       8. A method of manufacturing a semiconductor device according to  claim 7 , wherein said address information is shaped in a step of printing a mark on the surface of the resin mold. 
     
     
       9. A method of manufacturing a semiconductor device according to  claim 8 , wherein said address information and said mark are printed based on a laser printing scheme. 
     
     
       10. A method of manufacturing a semiconductor device according to  claim 7 , wherein said address information is shaped in a step different from a step of printing the mark on the resin mold. 
     
     
       11. A method of manufacturing a semiconductor device including processing steps of implementing the block molding with resin for a plurality of semiconductor chips which are mounted on a wiring substrate and thereafter dicing the wiring substrate into a plurality of resin-molded semiconductor devices,
 wherein said method further includes a step, which precedes said substrate dicing step, of appending address information of each of the resin-molded semiconductor devices to part of the wiring substrate,   wherein the wiring substrate has an upper surface, and a lower surface opposite to the upper surface,   wherein the semiconductor chips are mounted on the upper surface of the wiring substrate, and   wherein the address information of each of the resin-molded semiconductor devices is appended on the lower surface of the wiring substrate.    
     
     
       12. The method according to claim 11,
 wherein the block molding is implemented such that the resin covers the semiconductor chips and the upper surface of the wiring substrate.    
     
     
       13. The method according to claim 11,
 wherein the block molding is implemented such that the resin does not cover the address information of each of the resin-molded semiconductor devices.    
     
     
       14. The method according to claim 11,
 wherein the block molding is implemented such that the resin avoids contacting the address information of each of the resin-molded semiconductor devices.    
     
     
       15. The method according to claim 11,
 wherein the block molding is implemented such that the address information of each of the resin-molded semiconductor devices is located in an area spaced apart from where the resin is located.    
     
     
       16. The method according to claim 11,
 further including a step of forming a plurality of pads of each of the resin-molded semiconductor devices on the lower surface of the wiring substrate.    
     
     
       17. The method according to claim 16,
 wherein the address information in an area of the lower surface of the wiring substrate in which the pads are not formed.    
     
     
       18. The method according to claim 17,
 further including a step of forming a plurality of bumps on the pads, respectively.    
     
     
       19. The method according to claim 16,
 wherein the address information in an area of the lower surface of the wiring substrate that is spaced apart from areas in which the pads are formed.    
     
     
       20. The method according to claim 19,
 further including a step of forming a plurality of bumps on the pads, respectively.    
     
     
       21. The method according to claim 11,
 wherein the address information is comprised of a pattern made of a copper foil.    
     
     
       22. The method according to claim 21,
 wherein a pattern of the address information of each of the resin-molded semiconductor devices is different from one another.    
     
     
       23. The method according to claim 21,
 wherein the address information is comprised of alphanumeric characters.    
     
     
       24. The method according to claim 21,
 further including a step of forming a plurality of pads of each of the resin-molded semiconductor devices on the lower surface of the wiring substrate, and   wherein the pads and the address information are formed by etching the copper foil.    
     
     
       25. The method according to claim 11,
 further including a step of forming an index pattern of each of the resin-molded semiconductor devices on the lower surface of the wiring substrate.    
     
     
       26. The method according to claim 25,
 wherein the address information in an area of the lower surface of the wiring substrate in which the index pattern is not formed, and   wherein each of the address information and the index pattern is comprised of a pattern made of a copper foil.    
     
     
       27. The method according to claim 26,
 further including a step of forming a solder resist on the lower surface of the wiring substrate such that the solder resist covers the address information, and such that the solder resist exposes the index pattern.    
     
     
       28. The method according to claim 27,
 further including a step of forming a plurality of pads of each of the resin-molded semiconductor devices on the lower surface of the wiring substrate, and   wherein the solder resist is formed on the lower surface of the wiring substrate such that the solder resist covers the address information, and such that the solder resist exposes the index pattern and the pads.    
     
     
       29. The method according to claim 28,
 further including a step of forming a plurality of bumps on the pads, respectively.    
     
     
       30. The method according to claim 26,
 wherein the address information is comprised of alphanumeric characters.    
     
     
       31. The method according to claim 26,
 wherein the index pattern and the address information are formed by etching the copper foil.    
     
     
       32. The method according to claim 25,
 wherein the address information is formed in an area of the lower surface of the wiring substrate which is spaced apart from an area where the index pattern is formed, and   wherein each of the address information and the index pattern is comprised of a pattern made of a copper foil.    
     
     
       33. The method according to claim 32,
 further including a step of forming a solder resist on the lower surface of the wiring substrate such that the solder resist covers the address information, and such that the solder resist exposes the index pattern.    
     
     
       34. The method according to claim 33,
 further including a step of forming a plurality of pads of each of the resin-molded semiconductor devices on the lower surface of the wiring substrate, and   wherein the solder resist is formed on the lower surface of the wiring substrate such that the solder resist covers the address information, and such that the solder resist exposes the index pattern and the pads.    
     
     
       35. The method according to claim 34,
 further including a step of forming a plurality of bumps on the pads, respectively.    
     
     
       36. The method according to claim 32,
 wherein the address information is comprised of alphanumeric characters.    
     
     
       37. The method according to claim 32,
 wherein the index pattern and the address information are formed by etching the copper foil.

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