Semiconductor memory device and related method of programming

Abstract

A method of programming a nonvolatile memory device comprises applying a program voltage to a selected wordline to program selected memory cells, and performing a verify operation by applying a verify voltage to the selected wordline to determine the programming status of the selected memory cells. The verify operation applies the verify voltage to the selected wordline at least two different times to divide the selected memory cells into at least three regions corresponding to different threshold voltage ranges.

What is claimed is: 
     
       1. A method of programming a nonvolatile memory device, comprising:
 applying a program voltage to a selected wordline to program selected memory cells; and   performing a verify operation by applying a verify voltage to the selected wordline to determine the programming status of the selected memory cells,   wherein the verify operation applies the verify voltage to the selected wordline at least two different times to divide the selected memory cells into at least three regions corresponding to different threshold voltage ranges.   
     
     
       2. The method of  claim 1 , wherein the verify voltage is applied to the selected wordline at a constant level during the verify operation. 
     
     
       3. The method of  claim 1 , wherein the nonvolatile memory device is a flash memory device. 
     
     
       4. The method of  claim 1 , wherein the nonvolatile memory device is a multi-level cell flash memory device. 
     
     
       5. The method of  claim 1 , further comprising:
 applying different program voltages to selected bitlines connected to the selected memory cells based on the respective regions of the selected memory cells.   
     
     
       6. The method of  claim 1 , further comprising:
 applying the program voltage to the selected wordline with an incrementally increased level during successive iterations of an incremental step pulse programming loop.   
     
     
       7. The method of  claim 6 , wherein the incremental step pulse programming loop comprises a program operation for applying the program voltage to the selected wordline and the verify operation. 
     
     
       8. The method of  claim 1 , wherein the verify operation comprises:
 pre-charging a sense node and a bitline;   performing a develop operation of the sense node and the bitline while the sense node and the bitline are coupled together; and   sensing data of a selected memory cell connected to the bitline by sensing the voltage of the sense node.   
     
     
       9. The method of  claim 8 , wherein sensing of the data of the selected memory cell connected to the bitline comprises sensing the voltage of the sense node several times during one develop operation. 
     
     
       10. The method of  claim 8 , wherein sensing the data of the selected memory cell connected to the bitline comprises sensing the voltage of the sense node one time during one develop operation. 
     
     
       11. The method of  claim 8 , wherein pre-charging the sense node is performed simultaneously with transmission of sensed data. 
     
     
       12. The method of  claim 1 , wherein an upper most region among the at least three regions corresponds to memory cells having threshold voltages above a verify read voltage, and the method further comprises programming all of the memory cells above the verify read voltage using incremental step pulse programming. 
     
     
       13. The method of  claim 1 , wherein performing the verify operation comprises:
 detecting current flowing through the selected memory cells when the verify voltage is applied to the selected wordline at a first sensing time, and detecting current flowing through the selected memory cells when the verify voltage is applied to the selected wordline at a second sensing time.   
     
     
       14. The method of  claim 13 , further comprising:
 comparing the current flowing through the selected memory cells at the first sensing time with a first reference current to distinguish selected memory cells having threshold voltages in a first range from selected memory cells having threshold voltages above the first range.   
     
     
       15. The method of  claim 14 , further comprising:
 comparing the current flowing through the selected memory cells at the second sensing time with a second reference current to distinguish selected memory cells having threshold voltages in a second range above than the first range from selected memory cells having threshold voltages in a third range above the second range.   
     
     
       16. The method of  claim 14 , further comprising:
 during a program operation, applying a program inhibit voltage to bitlines connected to the selected memory cells within the third range and applying a ground voltage to bitlines connected to selected memory cells within the first range.   
     
     
       17. A method of programming a nonvolatile memory device, comprising:
 applying a first program voltage to a selected wordline to program selected memory cells included in the nonvolatile memory device;   performing a verify operation by applying a verify voltage to the selected wordline and by applying a pre-charging voltage to at least one of selected bitlines connected to the selected memory cells to determine a programming status of the selected memory cells, the verify operation including a first verify operation and a second verify operation following the first verify operation, wherein the verify operation applies the verify voltage to the selected wordline at least two different times to divide the selected memory cells into at least three regions corresponding to different threshold voltage ranges, the at least three regions including a first region, a second region and a third region;   applying a second program voltage higher than the first program voltage to the selected wordline after the performing the verify operation; and   based on a result of the first verify operation and a result of the second verify operation, applying a bit-line bias to a first bitline among the selected bitlines during the applying the second program voltage to the selected wordline, the first bitline being connected to a first memory cell included in the second region,   wherein the second region has a threshold voltage range between the first region and the third region;   the verify voltage and the pre-charging voltage is maintained constantly during the verify operation regardless of the result of the first verify operation, and   the bit-line bias applied to the first bitline is higher than a ground voltage and lower than a program-inhibit voltage.   
     
     
       18. The method of claim 17, wherein the first memory cell is sensed as an off cell at the first verify operation and as an on cell at the second verify operation. 
     
     
       19. The method of claim 18, wherein the at least two different times include a first time for a first sense node develop operation of the first verify operation and a second time for a second sense node develop operation of the second verify operation, the first time being shorter than the second time. 
     
     
       20. The method of claim 17, wherein the program-inhibit voltage is a power supply voltage. 
     
     
       21. The method of claim 20, wherein the ground voltage is applied to a second bitline among the selected bitlines during the applying the second program voltage to the selected wordline, the second bitline being connected to a second memory cell included in the first region having a lower threshold voltage range than the second region, and the second memory cell being sensed as an on-cell at the first verify operation. 
     
     
       22. The method of claim 21, wherein the program-inhibit voltage is applied to a third bitline among the selected bitlines during the applying the second program voltage to the selected wordline, the third bitline being connected to a third memory cell included in the third region having a higher threshold voltage range than the second region, and the third memory cell being sensed as an off-cell at the first verify operation and the second verify operation. 
     
     
       23. The method of claim 18, wherein the nonvolatile memory device includes a memory cell array,
 the memory cell array includes a first plurality of nonvolatile memory cells storing one bit of data and a second plurality of nonvolatile memory cells storing more than one bit of data, and   the selected memory cells are included in the second plurality of nonvolatile memory cells.   
     
     
       24. A method of programming a nonvolatile memory device, comprising:
 applying a first program voltage to a selected wordline to program selected memory cells included in the nonvolatile memory device;   performing a verify operation by applying a verify voltage to the selected wordline and by applying a pre-charging voltage to at least one of selected bitlines connected to the selected memory cells to determine a programming status of the selected memory cells, the verify operation including a first verify operation and a second verify operation following the first verify operation, wherein the verify operation applies the verify voltage to the selected wordline at least two different times to divide the selected memory cells into at least three regions corresponding to different threshold voltage ranges, the at least three regions including a first region, a second region and a third region, and the verify operation including a first verify operation and a second verify operation following the first verify operation;   applying a second program voltage higher than the first program voltage to the selected wordline after the performing the verify operation; and   applying a bit-line bias to a first bitline among the selected bitlines during the applying the second program voltage to the selected wordline, the first bitline being connected to a first memory cell included in the second region, the bit-line bias applied to the first bitline is higher than a ground voltage and lower than a power supply voltage, and the first memory cell being sensed as off-cell at the first verify operation and sensed as on-cell at the second verify operation;   wherein the at least two different times include a first time for a first sense node develop operation of the first verify operation and a second time for a second sense node develop operation of the second verify operation, the first time being shorter than the second time,   the second region has a threshold voltage range between the first region and the third region;   the verify voltage and the pre-charging voltage is maintained constantly during the verify operation regardless of a result of the first verify operation.   
     
     
       25. The method of claim 24, wherein the nonvolatile memory device includes a memory cell array,
 the memory cell array includes a first plurality of nonvolatile memory cells storing one bit of data and a second plurality of nonvolatile memory cells storing more than one bit of data, and   the selected memory cells are included in the second plurality of nonvolatile memory cells.   
     
     
       26. A method of programming a nonvolatile memory device, comprising:
 performing a first program loop including:
 applying a first program voltage to a selected wordline to program selected memory cells included in the nonvolatile memory device; and 
 performing a verify operation by applying a verify voltage to the selected wordline to determine a programming status of the selected memory cells, the verify operation including a first verify operation and a second verify operation following the first verify operation, and 
   performing a second program loop after the first program loop, the second program loop including:
 applying a second program voltage higher than the first program voltage to the selected wordline; and 
 based on a result of the verify operation, applying a bit-line voltage to a first bitline connected to a first memory cell during the applying the second program voltage to the selected wordline, the bit-line voltage being higher than a ground voltage and lower than a program-inhibit voltage, 
   wherein the verify operation applies the verify voltage to the selected wordline at least two different times to divide the selected memory cells into at least three regions corresponding to different threshold voltage ranges,   the at least two different times include a first time for the first verify operation and a second time for the second verify operation, the first time being different from the second time,   the at least three regions include a first region, a second region and a third region, the second region having a higher threshold voltage range than the first region, the second region having a lower threshold voltage range than the third region, and   the verify voltage is maintained at a constant level during the verify operation, the verify operation including:
 applying a pre-charging voltage to a first bitline among selected bitlines connected to the selected memory cells; 
 performing a first develop operation of a sense node while the sense node and the first bitline are coupled together during the first time; and 
 performing a first sensing operation to a first memory cell connected to the first bitline by sensing a first developed voltage of the sense node after the performing the first develop operation; 
 after the performing the first sensing operation, performing a second develop operation of the sense node while the sense node and the first bitline are coupled together during the second time; and 
 performing a second sensing operation to the first memory cell connected to the first bitline by sensing a second developed voltage of the sense node after the performing the second develop operation, 
 wherein the pre-charging voltage is maintained at a constant level during the verify operation regardless of a result of the first sensing operation, 
 the first memory cell is included in the second region, and 
 the first memory cell is sensed as off-cell at the first sensing operation and sensed as on-cell at the second sensing operation. 
   
     
     
       27. The method of claim 26, wherein the program-inhibit voltage is applied to a second bitline connected to a second memory cell among the selected memory cells during the applying the second program voltage to the selected wordline,
 the second memory cell is included in the third region, and   the second memory cell is sensed as an off-cell at the first sensing operation and the second sensing operation.   
     
     
       28. The method of claim 27, wherein the ground voltage is applied a third bitline connected to a third memory cell among the selected memory cells during the applying the second program voltage to the selected wordline,
 the third memory cell is included in the first region, and   the third memory cell is sensed as on-cell at the first sensing operation.   
     
     
       29. The method of claim 28, wherein the program-inhibit voltage is a power supply voltage. 
     
     
       30. The method of claim 26, wherein the nonvolatile memory device includes a memory cell array,
 the memory cell array includes a first plurality of nonvolatile memory cells storing one bit of data and a second plurality of nonvolatile memory cells storing more than one bit of data, and   the selected memory cells are included in the second plurality of nonvolatile memory cells.   
     
     
       31. A method of programming a nonvolatile memory device, comprising:
 applying a first program voltage to a selected wordline to program selected memory cells included in the nonvolatile memory device;   performing a verify operation by applying a verify voltage to the selected wordline and by applying a pre-charging voltage to at least one of selected bitlines connected to the selected memory cells to determine a programming status of the selected memory cells, the verify operation including a first verify operation and a second verify operation following the first verify operation, wherein the verify operation applies the verify voltage to the selected wordline at least two different times to divide the selected memory cells into at least three regions corresponding to different threshold voltage ranges, the at least three regions including a first region, a second region and a third region;   applying a second program voltage higher than the first program voltage to the selected wordline after the performing the verify operation; and   based on a result of the first verify operation and a result of the second verify operation, applying a bit-line bias to a first bitline among the selected bitlines during the applying the second program voltage to the selected wordline, the first bitline being connected to a first memory cell included in the second region,   wherein the second region has a threshold voltage range between the first region and the third region;   the pre-charging voltage is maintained constantly during the verify operation regardless of the result of the first verify operation, and   the bit-line bias applied to the first bitline is higher than a ground voltage and lower than a program-inhibit voltage.   
     
     
       32. The method of claim 31, wherein the first memory cell is sensed as off cell at the first verify operation and as an on cell at the second verify operation. 
     
     
       33. The method of claim 32, wherein the at least two different times include a first time for a first sense node develop operation of the first verify operation and a second time for a second sense node develop operation of the second verify operation, the first time being shorter than the second time. 
     
     
       34. The method of claim 31, wherein the program-inhibit voltage is a power supply voltage. 
     
     
       35. The method of claim 34, wherein the ground voltage is applied to a second bitline among the selected bitlines during the applying the second program voltage to the selected wordline, the second bitline being connected to a second memory cell included in the first region having a lower threshold voltage range than the second region, and the second memory cell being sensed as on-cell at the first verify operation. 
     
     
       36. The method of claim 35, wherein the program-inhibit voltage is applied to a third bitline among the selected bitlines during the applying the second program voltage to the selected wordline, the third bitline being connected to a third memory cell included in the third region having a higher threshold voltage range than the second region, and the third memory cell being sensed as off-cell at the first verify operation and the second verify operation. 
     
     
       37. The method of claim 31, wherein the verify voltage is maintained constantly during the verify operation regardless of the result of the first verify operation. 
     
     
       38. A method of programming a nonvolatile memory device, comprising:
 applying a first program voltage to a selected wordline to program selected memory cells included in the nonvolatile memory device;   performing a verify operation by applying a verify voltage to the selected wordline and by applying a pre-charging voltage to at least one of selected bitlines connected to the selected memory cells to determine a programming status of the selected memory cells, the verify operation including a first verify operation and a second verify operation following the first verify operation, wherein the verify operation applies the verify voltage to the selected wordline at least two different times to divide the selected memory cells into at least three regions corresponding to different threshold voltage ranges, the at least three regions including a first region, a second region and a third region;   applying a second program voltage higher than the first program voltage to the selected wordline after the performing the verify operation; and   based on a result of the first verify operation and a result of the second verify operation, applying a bit-line bias to a first bitline among the selected bitlines during the applying the second program voltage to the selected wordline, the first bitline being connected to a first memory cell included in the second region,   wherein the second region has a threshold voltage range between the first region and the third region;   the pre-charging voltage is not discharged during the verify operation regardless of the result of the first verify operation, and   the bit-line bias applied to the first bitline is higher than a ground voltage and lower than a program-inhibit voltage.   
     
     
       39. The method of claim 38, wherein the pre-charging voltage is not discharged to the ground voltage during the verify operation regardless of the result of the first verify operation. 
     
     
       40. The method of claim 39, wherein the pre-charging voltage is maintained constantly during the verify operation regardless of the result of the first verify operation. 
     
     
       41. The method of claim 40, wherein the verify voltage is maintained constantly during the verify operation regardless of the result of the first verify operation. 
     
     
       42. The method of claim 38, wherein the first memory cell is sensed as off cell at the first verify operation and as an on cell at the second verify operation. 
     
     
       43. The method of claim 39, wherein the at least two different times include a first time for a first sense node develop operation of the first verify operation and a second time for a second sense node develop operation of the second verify operation, the first time being shorter than the second time. 
     
     
       44. The method of claim 38, wherein the program-inhibit voltage is a power supply voltage. 
     
     
       45. The method of claim 41, wherein the ground voltage is applied to a second bitline among the selected bitlines during the applying the second program voltage to the selected wordline, the second bitline being connected to a second memory cell included in the first region having a lower threshold voltage range than the second region, and the second memory cell being sensed as on-cell at the first verify operation. 
     
     
       46. The method of claim 42, wherein the program-inhibit voltage is applied to a third bitline among the selected bitlines during the applying the second program voltage to the selected wordline, the third bitline being connected to a third memory cell included in the third region having a higher threshold voltage range than the second region, and the third memory cell being sensed as off-cell at the first verify operation and the second verify operation.