Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices

Abstract

A method for fabricating a low resistance, low inductance device for high current semiconductor flip-chip products. A structure is produced, which comprises a semiconductor chip with metallization traces, copper lines in contact with the traces, and copper bumps located in an orderly and repetitive arrangement on each line so that the bumps of one line are positioned about midway between the corresponding bumps of the neighboring lines. A substrate is provided which has elongated copper leads with first and second surfaces, the leads oriented at right angles to the lines. The first surface of each lead is connected to the corresponding bumps of alternating lines using solder elements. Finally, the assembly is encapsulated in molding compound so that the second lead surfaces remain un-encapsulated.

We claim: 
     
       1. A method for fabricating a low resistance, low inductance interconnection structure for high current semiconductor flip-chip products, comprising the steps of:
 providing a semiconductor wafer having metallization traces, the wafer surface protected by an overcoat, and windows in the overcoat, to expose portions of the metallization traces; 
 forming copper lines on the overcoat,; 
 contacting the metallization traces by filling the windows with metal; 
 depositing a layer of photo-imageable insulation material over the copper lines and the remaining wafer surface; 
 opening windows in the photo-imageable insulation material to expose portions of the copper lines, the locations of the windows selected in an orderly and repetitive arrangement on each copper line so that the windows of one line are positioned about midway between the corresponding windows of the neighboring lines; and 
 forming copper bumps in the windows, in contact with the lines. 
 
     
     
       2. The method according to  claim 1  further comprising the step of depositing a cap of solderable metal layers on each bump. 
     
     
       3. The method according to  claim 1  wherein the number and locations of the windows in the overcoat are selected as needed for the devices employing the metallization traces. 
     
     
       4. The method according to  claim 1  wherein the copper lines are oriented parallel to the metallization traces. 
     
     
       5. The method according to  claim 1  wherein the copper lines are oriented at right angles to the metallization traces. 
     
     
       6. The method according to  claim 1  wherein the step of forming copper lines comprises the steps of:
 depositing a barrier metal layer over the wafer surface; 
 depositing a seed metal layer over the barrier metal layer; 
 depositing a first photoresist layer over the seed metal layer in a height commensurate with the height of intended copper lines; 
 opening windows in the first photoresist layer so that the windows are shaped as the intended lines; 
 depositing copper to fill the photoresist windows and form copper lines; 
 removing the first photoresist layer; and 
 removing the portions of the adhesion and barrier layers, which are exposed after removing the first photoresist layer. 
 
     
     
       7. The method according to  claim 6 , wherein the step of depositing copper comprises an electroplating technique. 
     
     
       8. The method according to  claim 1  wherein the step of forming copper bumps comprises the steps of:
 depositing a barrier metal layer over the wafer surface; 
 depositing a seed metal layer over the barrier metal layer; 
 depositing a second photoresist layer over the seed metal layer in a height commensurate with the height of the intended copper bumps; 
 opening windows in the second photoresist layer in locations intended for copper bumps, and of a width commensurate with the width of the intended copper bumps; 
 filling the photoresist windows by depositing copper to form copper bumps; 
 removing the second photoresist layer; and 
 removing the portions of the adhesion and barrier layers, which are exposed after removing the second photoresist layer. 
 
     
     
       9. The method according the step to claim  8 , wherein the step of depositing copper comprises an electroplating technique. 
     
     
       10. The method according to  claim 8  further comprising the step of:
 depositing one or more solderable metal layers on the surface of the copper bump bumps, before removing the second photoresist layer. 
 
     
     
       11. The method according to  claim 10  wherein said solderable metal layers include a layer of nickel on the copper surface, followed by a layer of palladium on the nickel layer. 
     
     
       12. A method for fabricating a low resistance, low inductance interconnection device for high current semiconductor flip-chip products, comprising the steps of:
 providing a structure comprising a semiconductor chip having metallization traces, copper lines in contact with the traces, and copper bumps located in an orderly and repetitive arrangement on each copper line so that the copper bumps of one copper line are positioned about midway between the corresponding copper bumps of the neighboring copper lines; 
 providing a substrate having elongated copper leads with first and second surfaces, the leads oriented at right angles to the copper lines; 
 connecting the first surface of each copper lead to the corresponding copper bumps of alternating copper lines using solder elements; and 
 at least partially encapsulating the assembly in molding compound so that the second lead surfaces remain un-encapsulated. 
 
     
     
       13. The method according to  claim 12  wherein the substrate is a leadframe including copper. 
     
     
       14. A method for fabricating a low resistance, low inductance interconnection system for high current semiconductor flip-chip devices, comprising the steps of:
 providing a low resistance, low inductance interconnection device comprising:
 a semiconductor chip structure including copper lines in contact with chip metallization traces, and copper bumps located in an orderly and repetitive arrangement on each copper line, the copper bumps of one copper line positioned about midway between the corresponding copper bumps of the neighboring copper lines; 
 a substrate having elongated copper leads with first and second surfaces, the copper leads at right angles to the copper lines, the first lead surfaces connected to the corresponding copper bumps of alternating copper lines by solder elements; and 
 the chip structure and substrate at least partially encapsulated so that the second lead surfaces remain un-encapsulated; 
 
 providing a circuit board having copper contact pads parallel to the copper leads; and 
 attaching the second surface of the device leads to the board pads using solder layers. 
 
     
     
       15. A method comprising:
 providing a structure having:
 a semiconductor chip having metallization traces; 
 copper lines in electrical contact with the traces; and 
 copper bumps located in an orderly and repetitive arrangement on each line so that the bumps of one line are positioned about midway between the corresponding bumps of the neighboring lines; 
   providing a substrate having elongated copper leads with first and second surfaces, each lead oriented at an angle to the lines;   connecting the first surface of each lead to the corresponding bumps of alternating lines using solder elements; and   encapsulating portions of the structure and the substrate using an encapsulation process that encapsulates a plurality of assembled structure and substrate units.   
     
     
       16. A packaged integrated circuit (IC) product comprising:
 a plurality of metallization traces formed on a first substrate, wherein the metallization traces are generally in parallel to one another;   a plurality of conductive lines formed on the first substrate, wherein each conductive lines is in contact with and is at least partially coextensive with at least one of the metallization traces;   a plurality of conductive bumps formed on each of the conductive lines, wherein the conductive bumps for each line are arranged in an orderly and repetitive pattern such that each conductive bump is positioned about midway between the corresponding conductive bumps of each of its neighboring conductive lines;   a plurality of leads formed on a second substrate, wherein each lead is electrically connected to corresponding conductive bumps from alternating conductive lines on the first substrate, wherein each lead is oriented at an angle to each conductive line, and wherein each lead includes a second surface that is opposite the first surface; and   an encapsulation layer covering portions of the first substrate and second substrate.   
     
     
       17. The packaged IC product according to claim 16 wherein the conductive lines, the conductive bumps, and the leads further comprise copper. 
     
     
       18. The packaged IC product according to claim 17, wherein the angle is a right angle. 
     
     
       19. The packaged IC product according to claim 18 further comprising a solderable metal layer formed on the surface of the copper bump. 
     
     
       20. The packaged IC product according to claim 19 wherein the solderable metal layer includes a layer of nickel on the copper surface, followed by a layer of palladium on the nickel layer. 
     
     
       21. The packaged IC product according to claim 20 wherein the first substrate is a semiconductor wafer. 
     
     
       22. The packaged IC product according to claim 21 wherein the second substrate is a leadframe. 
     
     
       23. The packaged IC product according to claim 16, wherein the second surface of each of the leads is exposed following the formation of the encapsulation layer. 
     
     
       24. The method according to claim 12 wherein the copper lines further comprise top and bottom surfaces, and wherein the bottom surfaces are in contact with the traces, and wherein the step of providing the structure further comprises the step of providing an insulating layer that overlies the semiconductor chip between the copper lines and at least extends between the top and bottom surfaces of the copper lines. 
     
     
       25. The method according to claim 24 wherein the insulating layer has a thickness between approximately 10 and 20 μm. 
     
     
       26. The method according to claim 24 wherein the insulating layer further comprises a first insulating layer, and wherein the step of providing the structure further comprises providing a second insulating layer formed over at least a portion of the top surfaces of the copper lines. 
     
     
       27. The method according to claim 26 wherein the first insulating layer has a thickness between approximately 10 and 20 μm. 
     
     
       28. A method for fabricating a semiconductor flip-chip product, comprising the steps of:
 providing a semiconductor chip having metallization traces, copper lines connected to the traces, and plated copper bump structures located in an orderly and repetitive arrangement on each copper line;   providing an insulating layer that overlies the semiconductor chip and extends between the top and bottom surfaces of the copper lines and over at least a portion of the top surface of the copper lines;   providing a substrate having elongated copper leads with first and second surfaces;   electrically coupling the first surface of each copper lead to corresponding ones of the plated copper bump structures using solder elements;   at least partially encapsulating the semiconductor chip and the substrate; and   providing un-encapsulated portions of the second lead surfaces for further electrical attachment.   
     
     
       29. The method of claim 28 wherein the substrate comprises a metallic leadframe. 
     
     
       30. The method of claim 28 wherein the insulating layer is at least 10 μm thick.