Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices

Abstract

A method for fabricating a low resistance, low inductance device for high current semiconductor flip-chip products. A structure is produced, which comprises a semiconductor chip with metallization traces, copper lines in contact with the traces, and copper bumps located in an orderly and repetitive arrangement on each line so that the bumps of one line are positioned about midway between the corresponding bumps of the neighboring lines. A substrate is provided which has elongated copper leads with first and second surfaces, the leads oriented at right angles to the lines. The first surface of each lead is connected to the corresponding bumps of alternating lines using solder elements. Finally, the assembly is encapsulated in molding compound so that the second lead surfaces remain un-encapsulated.

We claim: 
     
       1. A method for fabricating a low resistance, low inductance interconnection structure for high current semiconductor flip-chip products, comprising the steps of:
 providing a semiconductor wafer having metallization traces, the wafer surface protected by an overcoat, and windows in the overcoat to expose portions of the metallization traces;   forming copper lines on the overcoat, contacting the traces by filling the windows with metal;   depositing a layer of photo-imageable insulation material over the lines and the remaining wafer surface;   opening windows in the insulation material to expose portions of the lines, the locations of the windows selected in an orderly and repetitive arrangement on each line so that the windows of one line are positioned about midway between the corresponding windows of the neighboring lines; and   forming copper bumps in the windows, in contact with the lines.   
     
     
       2. The method according to  claim 1  further comprising the step of depositing a cap of solderable metal layers on each bump. 
     
     
       3. The method according to  claim 1  wherein the number and locations of the windows in the overcoat are selected as needed for the devices employing the metallization traces. 
     
     
       4. The method according to  claim 1  wherein the copper lines are oriented parallel to the metallization traces. 
     
     
       5. The method according to  claim 1  wherein the copper lines are oriented at right angles to the metallization traces. 
     
     
       6. The method according to  claim 1  wherein the step of forming copper lines comprises the steps of:
 depositing a barrier metal layer over the wafer surface; 
 depositing a seed metal layer over the barrier metal layer; 
 depositing a first photoresist layer over the seed metal layer in a height commensurate with the height of intended copper lines; 
 opening windows in the photoresist layer so that the windows are shaped as the intended lines; 
 depositing copper to fill the photoresist windows and form copper lines; 
 removing the first photoresist layer; and 
 removing the portions of the adhesion and barrier layers, which are exposed after removing the first photoresist layer. 
 
     
     
       7. The method according to  claim 6 , wherein the step of depositing copper comprises an electroplating technique. 
     
     
       8. The method according to  claim 1  wherein the step of forming copper bumps comprises the steps of:
 depositing a barrier metal layer over the wafer surface; 
 depositing a seed metal layer over the barrier metal layer; 
 depositing a second photoresist layer over the seed metal layer in a height commensurate with the height of the intended copper bumps; 
 opening windows in the photoresist layer in locations intended for copper bumps, and of a width commensurate with the width of the intended copper bumps; 
 filling the photoresist windows by depositing copper to form copper bumps; 
 removing the second photoresist layer; and 
 removing the portions of the adhesion and barrier layers, which are exposed after removing the second photoresist layer. 
 
     
     
       9. The method according the step  8 , wherein the step of depositing copper comprises an electroplating technique. 
     
     
       10. The method according to  claim 8  further comprising the step of:
 depositing one or more solderable metal layers on the surface of the copper bump, before removing the second photoresist layer. 
 
     
     
       11. The method according to  claim 10  wherein said solderable metal layers include a layer of nickel on the copper surface, followed by a layer of palladium on the nickel layer. 
     
     
       12. A method for fabricating a low resistance, low inductance interconnection device for high current semiconductor flip-chip products, comprising the steps of:
 providing a structure comprising a semiconductor chip having metallization traces, copper lines in contact with the traces, and copper bumps located in an orderly and repetitive arrangement on each line so that the bumps of one line are positioned about midway between the corresponding bumps of the neighboring lines;   providing a substrate having elongated copper leads with first and second surfaces, the leads oriented at right angles to the lines;   connecting the first surface of each lead to the corresponding bumps of alternating lines using solder elements; and   encapsulating the assembly in molding compound so that the second lead surfaces remain un-encapsulated.   
     
     
       13. The method according to  claim 12  wherein the substrate is a leadframe including copper. 
     
     
       14. A method for fabricating a low resistance, low inductance interconnection system for high current semiconductor flip-chip devices, comprising the steps of:
 providing a low resistance, low inductance interconnection device comprising:
 a semiconductor chip structure including copper lines in contact with chip metallization traces, and copper bumps located in an orderly and repetitive arrangement on each line, the bumps of one line positioned about midway between the corresponding bumps of the neighboring lines; 
 a substrate having elongated copper leads with first and second surfaces, the leads at right angles to the lines, the first lead surfaces connected to the corresponding bumps of alternating lines by solder elements; and 
 the chip structure and substrate encapsulated so that the second lead surfaces remain un-encapsulated; 
   providing a circuit board having copper contact pads parallel to the leads; and   attaching the second surface of the device leads to the board pads using solder layers.   
     
     
       15. A method comprising:
 providing a structure having:   a semiconductor chip having metallization traces;   copper lines in contact with the traces; and   copper bumps located in an orderly and repetitive arrangement on each line so that the bumps of one line are positioned about midway between the corresponding bumps of the neighboring lines;   providing a substrate having elongated copper leads with first and second surfaces, each lead oriented at a right angle to the lines;   connecting the first surface of each lead to the corresponding bumps of alternating lines using solder elements; and   encapsulating portions of the structure and the substrate, wherein the second surface of each of the leads is un-encapsulated.   
     
     
       16. The method according to claim 15 wherein the substrate is a leadframe including copper. 
     
     
       17. A method comprising:
 forming a plurality of metallization traces on a first substrate, wherein the metallization traces are generally in parallel to one another;   forming a plurality of conductive lines on the first substrate, wherein each conductive line is in contact with and is at least partially coextensive with at least one of the metallization traces;   forming a plurality of conductive bumps on each of the conductive lines, wherein the conductive bumps for each line are arranged in an orderly and repetitive pattern such that each conductive bump is positioned about midway between the corresponding conductive bumps of each of its neighboring conductive lines;   forming a plurality of leads on a second substrate, wherein each lead includes a first surface and an opposite second surface;   electrically connecting the first surface of each of the plurality of leads to corresponding conductive bumps from alternating conductive lines on the first substrate, wherein each lead is oriented at an angle to each conductive line; and   forming an encapsulation layer over portions of the first substrate and the second substrate, wherein the second surface of each of the of the leads is not covered by the encapsulation layer.   
     
     
       18. The method according to claim 17 wherein the conductive lines, the conductive bumps, and the leads further comprise copper. 
     
     
       19. The method according to claim 18, wherein the angle is a right angle. 
     
     
       20. The method according to claim 19 wherein the step of forming a plurality of conductive lines further comprises the steps of:
 depositing a barrier metal layer over a surface of the substrate;   depositing a seed metal layer over the barrier metal layer;   depositing a first photoresist layer over the seed metal layer in a height commensurate with the height of intended copper lines;   opening windows in the photoresist layer so that the windows are shaped as the intended lines;   depositing copper to fill the photoresist windows;   removing the first photoresist layer; and   removing the portions of the adhesion and barrier layers, which are exposed after removing the first photoresist layer.   
     
     
       21. The method according to claim 20, wherein the step of depositing copper comprises an electroplating technique. 
     
     
       22. The method according to claim 19 wherein the step of forming the plurality of conductive bumps further comprises the steps of:
 depositing a barrier metal layer over the substrate;   depositing a seed metal layer over the barrier metal layer;   depositing a second photoresist layer over the seed metal layer in a height commensurate with the height of the intended conductive bumps;   opening windows in the photoresist layer in locations intended for conductive bumps, and of a width commensurate with the width of the intended conductive bumps;   filling the photoresist windows by depositing conductive to form conductive bumps; removing the second photoresist layer; and   removing the portions of the adhesion and barrier layers, which are exposed after removing the second photoresist layer.   
     
     
       23. The method according the claim 22 wherein the step of depositing copper comprises an electroplating technique. 
     
     
       24. The method according to claim 23 further comprising the step of depositing a solderable metal layer on the surface of the copper bump, before removing the second photoresist layer. 
     
     
       25. The method according to claim 24 wherein the solderable metal layer includes a layer of nickel on the copper surface, followed by a layer of palladium on the nickel layer. 
     
     
       26. The method according to claim 19 wherein the first substrate is formed from a semiconductor wafer. 
     
     
       27. The method according to claim 26 wherein the second substrate is a leadframe. 
     
     
       28. The method according to claim 17 wherein the first substrate is formed from a semiconductor wafer. 
     
     
       29. The method according to claim 28 wherein the second substrate is a leadframe. 
     
     
       30. The method according to claim 17 wherein the step of electrically connecting further comprises soldering the first surface of each of a plurality of leads to corresponding conductive bumps from alternating conductive lines on the first substrate.