Package board having internal terminal interconnection and semiconductor package employing the same

Abstract

A package board is provided. The package board includes a board body having a front surface and a back surface. A first power pad, a first ground pad, a first signal pad, a first internal terminal pad and a second internal terminal pad are disposed on the front surface of the board body, and a second power pad, a second ground pad and a second signal pad are disposed on the back surface of the board body. The second power pad, the second ground pad and the second signal pad are electrically connected to the first power pad, the first ground pad and the first signal pad, respectively. An internal terminal interconnection is provided in a bulk region of the board body or on a surface of the board body. The internal terminal interconnection electrically connects the first internal terminal pad to the second internal terminal pad. A semiconductor package employing the package board is also provided.

What is claimed is: 
     
       1. A package board comprising:
 a board body having a front surface and a back surface;   a first power pad, a first ground pad, a first signal pad, a first internal terminal pad and a second internal terminal pad disposed on the front surface of the board body;   a second power pad, a second ground pad and a second signal pad disposed on the back surface of the board body, the second power pad, the second ground pad and the second signal pad being electrically connected to the first power pad, the first ground pad and the first signal pad, respectively; and   an internal terminal interconnection disposed in a bulk region of the board body or on a surface of the board body to electrically connect the first internal terminal pad to the second internal terminal pad,   wherein the first internal terminal pad and the second internal terminal pad are electrically insulated from the first power pad, the first ground pad and the first signal pad.   
     
     
       2. The package board according to  claim 1 , further comprising a common power interconnection disposed in the bulk region of the board body or on the surface of the board body and electrically connected to the first and second power pads. 
     
     
       3. The package board according to  claim 2 , wherein the internal terminal interconnection is disposed across the common power interconnection and electrically insulated from the common power interconnection. 
     
     
       4. The package board according to  claim 1 , further comprising a common ground interconnection disposed in the bulk region of the board body or on the surface of the board body and electrically connected to the first and second ground pads. 
     
     
       5. The package board according to  claim 4 , wherein the internal terminal interconnection is disposed across the common ground interconnection and electrically insulated from the common ground interconnection. 
     
     
       6. The package board according to  claim 1 , wherein the first power pad, the first ground pad and the first signal pad are electrically connected to the second power pad, the second ground pad and the second signal pad, respectively, through first, second and third holes penetrating the board body. 
     
     
       7. The package board according to  claim 1 , wherein the first internal terminal pad and the second internal terminal pad are directly connected to a first internal bonding pad and a second internal bonding pad of a semiconductor chip to be mounted on the front surface of the board body. 
     
     
       8. The package board according to  claim 2 , wherein the internal terminal interconnection and the common power interconnection are electrically insulated from each other. 
     
     
       9. The package board according to  claim 1 , wherein the first internal terminal pad and the second internal terminal pad are only disposed on the front surface of the board body. 
     
     
       10. A semiconductor package comprising:
 a board body having a front surface and a back surface;   a first power pad, a first ground pad, a first signal pad, a first internal terminal pad and a second internal terminal pad disposed on the front surface of the board body;   a second power pad, a second ground pad and a second signal pad disposed on the back surface of the board body, the second power pad, the second ground pad and the second signal pad being electrically connected to the first power pad, the first ground pad and the first signal pad, respectively;   a power ball, a ground ball and a signal ball that are in contact with the second power pad, the second ground pad and the second signal pad, respectively;   an internal terminal interconnection disposed in a bulk region of the board body or on a surface of the board body to electrically connect the first internal terminal pad to the second internal terminal pad;   a semiconductor chip mounted on the front surface of the board body, the semiconductor chip having an external power bonding pad, an external ground bonding pad, an external signal bonding pad, a first internal bonding pad and a second internal bonding pad; and   an external power connector, an external ground connector, an external signal connector, a first internal connector and a second internal connector electrically connecting the first power pad, the first ground pad, the first signal pad, the first internal terminal pad and the second internal terminal pad to the external power bonding pad, the external ground bonding pad, the external signal bonding pad, the first internal bonding pad and the second internal bonding pad, respectively,   wherein the first internal terminal pad and the second internal terminal pad are electrically insulated from the first power pad, the first ground pad and the first signal pad.   
     
     
       11. The package according to  claim 10 , further comprising a common power interconnection disposed in the bulk region of the board body or on the surface of the board body and electrically connected to the first and second power pads. 
     
     
       12. The package according to  claim 10 , further comprising a common ground interconnection disposed in the bulk region of the board body or on the surface of the board body and electrically connected to the first and second ground pads. 
     
     
       13. The package according to  claim 10 , wherein the first power pad, the first ground pad and the first signal pad are electrically connected to the second power pad, the second ground pad and the second signal pad, respectively, through first, second and third holes penetrating the board body. 
     
     
       14. The package according to  claim 10 , wherein the first internal bonding pad is electrically connected to an output terminal of an internal power generator of the semiconductor chip, and wherein the second internal bonding pad is electrically connected to a power terminal of any one of one or more internal circuits of the semiconductor chip. 
     
     
       15. The package according to  claim 10 , wherein the semiconductor chip is a flip chip. 
     
     
       16. The package according to  claim 15 , wherein the external power connector, the external ground connector, the external signal connector, the first internal connector and the second internal connector are flip chip bumps. 
     
     
       17. The semiconductor package according to  claim 11 , wherein the first internal connector and the second internal connector are electrically insulated from the common power interconnection. 
     
     
       18. A semiconductor package comprising:
 a board body having a front surface and a back surface;   a first power pad, a first ground pad, a first signal pad, a first internal terminal pad and a second internal terminal pad disposed on the front surface of the board body;   a second power pad, a second ground pad and a second signal pad disposed on the back surface of the board body, the second power pad, the second ground pad and the second signal pad being electrically connected to the first power pad, the first ground pad and the first signal pad, respectively;   a power ball, a ground ball and a signal ball that are in contact with the second power pad, the second ground pad and the second signal pad, respectively;   an internal terminal interconnection disposed in a bulk region of the board body or on a surface of the board body to electrically connect the first internal terminal pad to the second internal terminal pad;   a semiconductor chip mounted on the front surface of the board body, the semiconductor chip having an external power bonding pad, an external ground bonding pad, an external signal bonding pad, a first internal bonding pad and a second internal bonding pad; and   an external power connector, an external ground connector, an external signal connector, a first internal connector and a second internal connector electrically connecting the first power pad, the first ground pad, the first signal pad, the first internal terminal pad and the second internal terminal pad to the external power bonding pad, the external ground bonding pad, the external signal bonding pad, the first internal bonding pad and the second internal bonding pad, respectively,   wherein the semiconductor chip comprises:   a semiconductor substrate;   internal circuits formed at the semiconductor substrate;   an insulating layer covering the internal circuits and the semiconductor substrate;   an external power chip pad, an external ground chip pad, an external signal chip pad, a first internal chip pad and a second internal chip pad disposed on the insulating layer and electrically connected to the internal circuits;   a dielectric layer covering the insulating layer and the chip pads; and   a power line, a ground line, a signal line, a first interconnection and a second interconnection redistributed on the dielectric layer and electrically connected to the external power chip pad, the external ground chip pad, the external signal chip pad, the first internal chip pad and the second internal chip pad, respectively,   wherein a portion of the redistributed power line, a portion of the redistributed ground line, a portion of the redistributed signal line, a portion of the first interconnection and a portion of the second interconnection correspond to the external power bonding pad, the external ground bonding pad, the external signal bonding pad, the first internal bonding pad and the second internal bonding pad, respectively.   
     
     
       19. The package according to  claim 18 , further comprising an internal interconnection disposed on or in the insulating layer, wherein the internal interconnection electrically connects the first internal chip pad to the second internal chip pad. 
     
     
       20. The package according to  claim 18 , wherein the one or more internal circuits are configured as a DRAM circuit. 
     
     
       21. The package according to  claim 20 , wherein the DRAM circuit comprises a well bias circuit, a high voltage generator and a plate electrode voltage generator. 
     
     
       22. The package according to  claim 21 , wherein one of the first internal chip pad and the second internal chip pad is electrically connected to an output terminal of any one of the well bias circuit, the high voltage generator and the plate electrode voltage generator. 
     
     
       23. The package according to  claim 18 , further comprising a redistributed internal interconnection provided on the dielectric layer to electrically connect the first internal bonding pad to the second internal bonding pad. 
     
     
       24. A semiconductor package comprising:
 a package board comprising:
 a board body having a front surface and a back surface; 
 a first power pad, a first ground pad, a first signal pad, and at least three internal terminal pads disposed on the front surface of the board body, the at least three internal terminal pads being configured to provide an internal power delivery function; 
 a second power pad, a second ground pad and a second signal pad disposed on the back surface of the board body, the second power pad, the second ground pad and the second signal pad being electrically connected to the first power pad, the first ground pad and the first signal pad, respectively; and 
 an internal terminal interconnection disposed in a bulk region of the board body or on the front surface of the board body to electrically connect the at least three internal terminal pads; and 
   a semiconductor chip mounted on the package board and including an internal power generator and an internal circuit,   wherein:
 the at least three internal terminal pads are electrically insulated from remaining pads configured to provide a function other than the internal power delivery function, the remaining pads including the first power pad, the first ground pad, the first signal pad, the second power pad, the second ground pad and the second signal pad, 
 the internal terminal interconnection is connected to the semiconductor chip through the at least three internal terminal pads, 
 one of the at least three internal terminal pads is electrically connected to an output terminal of the internal power generator, 
 another of the at least three internal terminal pads is electrically connected to a power terminal of the internal circuit, 
 the internal terminal interconnection is not electrically connected with conductive elements disposed on the back surface of the board body, 
 the semiconductor chip further comprises an internal interconnection electrically connecting the output terminal of the internal power generator and the power terminal of the internal circuit through a path fully within the semiconductor chip, and 
 a thickness of the internal terminal interconnection is greater than a thickness of the internal interconnection. 
   
     
     
       25. The semiconductor package of claim 24, wherein the internal terminal interconnection is physically connected to the semiconductor chip through the at least three internal terminal pads. 
     
     
       26. The semiconductor package of claim 24, wherein the at least three internal terminal pads are electrically connected to at least three internal bonding pads of the semiconductor chip. 
     
     
       27. The semiconductor package of claim 24, wherein the at least three internal terminal pads are disposed only on the front surface of the board body. 
     
     
       28. The semiconductor package of claim 24, wherein the internal terminal interconnection is configured to receive internal power from the internal power generator in the semiconductor chip. 
     
     
       29. The semiconductor package of claim 24, further comprising:
 a first conductive line straightly passing through the board body to connect the first power pad to the second power pad;   a second conductive line straightly passing through the board body to connect the first ground pad to the second ground pad; and   a third conductive line straightly passing through the board body to connect the first signal pad to the second signal pad.   
     
     
       30. The semiconductor package of claim 24, wherein the internal terminal interconnection does not encircle any of the at least three internal terminal pads. 
     
     
       31. The semiconductor package of claim 24, wherein the internal terminal interconnection does not have a spiral geometry. 
     
     
       32. The semiconductor package of claim 24, wherein the internal terminal interconnection does not operate as an inductor. 
     
     
       33. The semiconductor package of claim 24, wherein the internal terminal interconnection circumvents other conductive structures when connecting between the at least three internal terminal pads. 
     
     
       34. A semiconductor package comprising:
 a package board comprising:
 a board body having a front surface and a back surface; 
 a first power pad, a first ground pad, a first signal pad, and at least three internal terminal pads disposed on the front surface of the board body, the at least three internal terminal pads that include a first internal terminal pad and a second internal terminal pad being configured to provide an internal power delivery function; 
 a second power pad, a second ground pad and a second signal pad disposed on the back surface of the board body, the second power pad, the second ground pad and the second signal pad being electrically connected to the first power pad, the first ground pad and the first signal pad, respectively; and 
 an internal terminal interconnection disposed in a bulk region of the board body or on the front surface of the board body to electrically connect the first internal terminal pad to the second internal terminal pad; and 
   a semiconductor chip mounted on the package board and including an internal power generator and an internal circuit,   wherein:
 the at least three internal terminal pads are electrically insulated from the first power pad, the first ground pad and the first signal pad, 
 the internal terminal interconnection is connected to the semiconductor chip through the at least three internal terminal pads, 
 the internal terminal interconnection is not electrically connected with conductive elements disposed on the back surface of the board body, 
 the at least three internal terminal pads include a first internal terminal pad and a second internal terminal pad, 
 the first internal terminal pad is electrically connected to an output terminal of the internal power generator, 
 the second internal terminal pad is electrically connected to a power terminal of the internal circuit, 
 the internal terminal interconnection does not operate as an inductor, 
 the semiconductor chip further comprises an internal interconnection electrically connecting the output terminal of the internal power generator and the power terminal of the internal circuit through a path fully within the semiconductor chip, and 
 a thickness of the internal terminal interconnection is greater than a thickness of the internal interconnection. 
   
     
     
       35. The semiconductor package of claim 34, wherein the internal terminal interconnection is configured to receive internal power from the internal power generator. 
     
     
       36. The semiconductor package of claim 34, wherein the internal terminal interconnection does not encircle any of the at least three internal terminal pads. 
     
     
       37. The semiconductor package of claim 34, wherein the internal terminal interconnection does not have a spiral geometry. 
     
     
       38. The semiconductor package of claim 34, wherein the internal terminal interconnection circumvents other conductive structures when connecting between the at least three internal terminal pads. 
     
     
       39. A semiconductor device comprising:
 a package board comprising:
 a board body having a front surface and a back surface; 
 a first power pad, a first ground pad, a first signal pad, and at least three internal terminal pads disposed on the front surface of the board body; 
 a second power pad, a second ground pad and a second signal pad disposed on the back surface of the board body, the second power pad, the second ground pad and the second signal pad being electrically connected to the first power pad, the first ground pad and the first signal pad, respectively; and 
 an internal terminal interconnection disposed in a bulk region of the board body or on the front surface of the board body to electrically connect the at least three internal terminal pads, the at least three internal terminal pads being electrically insulated from the first power pad, the first ground pad and the first signal pad; and 
   a semiconductor chip mounted on the package board and including an internal power generator and an internal circuit,   wherein:
 the internal terminal interconnection is connected to the semiconductor chip through the at least three internal terminal pads; and 
 the internal terminal interconnection is not electrically connected with conductive elements disposed on the back surface of the board body, 
 the internal terminal interconnection does not encircle any of the at least three internal terminal pads, 
 a power terminal of the internal circuit is electrically connected to one of the at least three internal terminal pads, 
 the internal power generator is electrically connected to another of the at least three internal terminal pads, 
 the internal power generator outputs an internal power voltage through an output terminal which is applied to the internal circuit, 
 the internal terminal interconnection does not have a spiral geometry, 
 the semiconductor chip further comprises an internal interconnection electrically connecting the output terminal of the internal power generator and the power terminal of the internal circuit through a path fully within the semiconductor chip, and 
 a thickness of the internal terminal interconnection is greater than a thickness of the internal interconnection. 
   
     
     
       40. The semiconductor device of claim 39, wherein the internal terminal interconnection does not operate as an inductor. 
     
     
       41. The semiconductor device of claim 39, wherein the internal terminal interconnection circumvents other conductive structures when connecting between the at least three internal terminal pads. 
     
     
       42. The semiconductor device of claim 39, wherein the internal terminal interconnection does not have any shielding lines extending in parallel with the internal terminal interconnection. 
     
     
       43. The semiconductor device of claim 39, wherein the internal terminal interconnection horizontally extends to directly connect one of the at least three internal terminal pads with another of the at least three internal terminal pads. 
     
     
       44. The semiconductor device of claim 39, wherein no interconnections are sides of the internal terminal interconnection between one of the at least three internal terminal pads and another of the at least three internal terminal pads so that the internal terminal interconnection has a single line. 
     
     
       45. The semiconductor device of claim 39, further comprising:
 a common ground interconnection disposed in the bulk region of the board body and electrically connected to the first and second ground pads,   wherein the internal terminal interconnection is disposed at a level different than the common ground interconnection so that the front surface of the board body is closer to the internal terminal interconnection than the common ground interconnection.   
     
     
       46. A semiconductor package comprising:
 a package board including:
 a board body having a front surface and a back surface; 
 a first power pad, a first ground pad, a first signal pad, a first internal terminal pad and a second internal terminal pad disposed on the front surface of the board body, the first and second internal terminal pads being configured to provide an internal power delivery function; 
 a second power pad, a second ground pad and a second signal pad disposed on the back surface of the board body, the second power pad, the second ground pad and the second signal pad being electrically connected to the first power pad, the first ground pad and the first signal pad, respectively; and 
 an internal terminal interconnection disposed in a bulk region of the board body or on the front surface of the board body to electrically connect the first internal terminal pad and the second internal terminal pad; and 
   a semiconductor chip mounted on the package board, and including an internal power generator, an internal circuit, a first internal chip pad and a second internal chip pad,   wherein:
 the first internal terminal pad is electrically connected to the first internal chip pad, 
 the second internal terminal pad is electrically connected to the second internal chip pad, 
 the first and second internal terminal pads are electrically insulated from the first power pad, the first ground pad and the first signal pad, 
 the first internal chip pad is electrically connected to an output terminal of the internal power generator, 
 the second internal chip pad is electrically connected to a power terminal of the internal circuit, 
 the semiconductor chip further comprises an internal interconnection electrically connecting the output terminal of the internal power generator and the power terminal of the internal circuit through a path fully within the semiconductor chip, and 
 a thickness of the internal terminal interconnection is greater than a thickness of the internal interconnection. 
   
     
     
       47. The semiconductor package of claim 46, wherein the semiconductor package includes a flash memory. 
     
     
       48. The semiconductor package of claim 46, wherein the internal terminal interconnection is not electrically connected with conductive elements disposed on the back surface of the board body. 
     
     
       49. The semiconductor package of claim 46, wherein the internal terminal interconnection does not have a spiral geometry. 
     
     
       50. The semiconductor package of claim 46, wherein the internal terminal interconnection does not operate as an inductor. 
     
     
       51. The semiconductor package of claim 46, wherein the internal terminal interconnection circumvents other conductive structures when connecting between the first internal terminal pad and the second internal terminal pad. 
     
     
       52. The semiconductor package of claim 46, wherein the internal terminal interconnection does not encircle the first and second internal terminal pads. 
     
     
       53. A semiconductor package comprising:
 a package board including:
 a board body having a front surface and a back surface; 
 a first power pad, a first ground pad, a first signal pad, a first internal terminal pad and a second internal terminal pad disposed on the front surface of the board body, the first and second internal terminal pads being configured to provide an internal power delivery function; 
 a second power pad, a second ground pad and a second signal pad disposed on the back surface of the board body, the second power pad, the second ground pad and the second signal pad being electrically connected to the first power pad, the first ground pad and the first signal pad, respectively; and 
 an internal terminal interconnection disposed in a bulk region of the board body or on the front surface of the board body to electrically connect the first internal terminal pad and the second internal terminal pad; and 
   a semiconductor chip mounted on the package board, and including an internal power generator, an internal circuit, a first internal chip pad and a second internal chip pad,   wherein:
 the first internal terminal pad is electrically connected to the first internal chip pad, 
 the second internal terminal pad is electrically connected to the second internal chip pad, 
 the first internal chip pad is electrically connected to an output terminal of the internal power generator, 
 the second internal chip pad is electrically connected to a power terminal of the internal circuit, 
 the first and second internal terminal pads are electrically insulated from the first power pad, the first ground pad and the first signal pad, 
 the internal terminal interconnection is not electrically connected with conductive elements disposed on the back surface of the board body, 
 the semiconductor chip further comprises an internal interconnection electrically connecting the output terminal of the internal power generator and the power terminal of the internal circuit through a path fully within the semiconductor chip, and 
 a thickness of the internal terminal interconnection is greater than a thickness of the internal interconnection. 
   
     
     
       54. The semiconductor package of claim 53, wherein the semiconductor package includes a flash memory. 
     
     
       55. The semiconductor package of claim 53, wherein the internal terminal interconnection does not have a spiral geometry. 
     
     
       56. The semiconductor package of claim 53, wherein the internal terminal interconnection does not operate as an inductor. 
     
     
       57. The semiconductor package of claim 53, wherein the internal terminal interconnection circumvents other conductive structures when connecting between the first internal terminal pad and the second internal terminal pad. 
     
     
       58. The semiconductor package of claim 53, wherein the internal terminal interconnection does not encircle the first and second internal terminal pads. 
     
     
       59. A semiconductor package comprising:
 a package board including:
 a board body having a front surface and a back surface; 
 a first power pad, a first ground pad, a first signal pad, a first internal terminal pad and a second internal terminal pad disposed on the front surface of the board body, the first and second internal terminal pads being configured to provide an internal power delivery function; 
 a second power pad, a second ground pad and a second signal pad disposed on the back surface of the board body, the second power pad, the second ground pad and the second signal pad being electrically connected to the first power pad, the first ground pad and the first signal pad, respectively; and 
 an internal terminal interconnection disposed in a bulk region of the board body or on the front surface of the board body to electrically connect the first internal terminal pad and the second internal terminal pad; and 
   a semiconductor chip mounted on the package board, and including an internal power generator, an internal circuit, a first internal chip pad and a second internal chip pad,   wherein:
 the first internal terminal pad is electrically connected to the first internal chip pad, 
 the second internal terminal pad is electrically connected to the second internal chip pad, 
 the first and second internal terminal pads are electrically insulated from the first power pad, the first ground pad and the first signal pad, 
 the first internal chip pad is electrically connected to an output terminal of the internal power generator, and 
 the second internal chip pad is electrically connected to a power terminal of the internal circuit, 
 the internal power generator outputs an internal power voltage which is applied to the internal circuit, 
 the internal terminal interconnection does not have a spiral geometry, 
 the semiconductor chip further comprises an internal interconnection electrically connecting the output terminal of the internal power generator and the power terminal of the internal circuit through a path fully within the semiconductor chip; and 
 a thickness of the internal terminal interconnection is greater than a thickness of the internal interconnection. 
   
     
     
       60. The semiconductor package of claim 59, wherein the semiconductor package includes a flash memory. 
     
     
       61. The semiconductor package of claim 59, wherein the internal terminal interconnection does not operate as an inductor. 
     
     
       62. The semiconductor package of claim 59, wherein the internal terminal interconnection circumvents other conductive structures when connecting between the first internal terminal pad and the second internal terminal pad. 
     
     
       63. The semiconductor package of claim 59, wherein the internal terminal interconnection does not encircle the first and second internal terminal pads. 
     
     
       64. A semiconductor device comprising:
 a package board including:
 a board body having a front surface and a back surface; 
 a first power pad, a first ground pad, a first signal pad, a first internal terminal pad and a second internal terminal pad disposed on the front surface of the board body, the first and second internal terminal pads being configured to provide an internal power delivery function; 
 a second power pad, a second ground pad and a second signal pad disposed on the back surface of the board body, the second power pad, the second ground pad and the second signal pad being electrically connected to the first power pad, the first ground pad and the first signal pad, respectively; and 
 an internal terminal interconnection disposed in a bulk region of the board body or on the front surface of the board body to electrically connect the first internal terminal pad and the second internal terminal pad; and 
   a semiconductor chip mounted on the package board, and including a first internal power generator, a second internal power generator, a first internal circuit, a second internal circuit, a first internal chip pad and a second internal chip pad,   wherein:
 the first internal terminal pad is electrically connected to the first internal chip pad, 
 the second internal terminal pad is electrically connected to the second internal chip pad, 
 the first and second internal terminal pads are electrically insulated from the first power pad, the first ground pad and the first signal pad, 
 the first internal chip pad is electrically connected to an output terminal of the first internal power generator, 
 the second internal chip pad is electrically connected to an output terminal of the second internal power generator, 
 the output terminal of the first internal power generator is electrically connected to a power terminal of the first internal circuit, 
 the output terminal of the second internal power generator is electrically connected to a power terminal of the second internal circuit, 
 the semiconductor chip further comprises a first internal interconnection electrically connecting the output terminal of the first internal power generator and the power terminal of the first internal circuit through a path fully within the semiconductor chip, 
 the semiconductor chip further comprises a second internal interconnection electrically connecting the output terminal of the second internal power generator and the power terminal of the second internal circuit through a path fully within the semiconductor chip, and 
 a thickness of the internal terminal interconnection is greater than a thickness of the first and second internal interconnections. 
   
     
     
       65. The semiconductor device of claim 64, further comprising a flash memory. 
     
     
       66. The semiconductor device of claim 64, wherein the internal terminal interconnection is not electrically connected with conductive elements disposed on the back surface of the board body. 
     
     
       67. The semiconductor device of claim 64, wherein the internal terminal interconnection does not have a spiral geometry. 
     
     
       68. The semiconductor device of claim 64, wherein the internal terminal interconnection does not operate as an inductor. 
     
     
       69. The semiconductor device of claim 64, wherein the internal terminal interconnection circumvents other conductive structures when connecting between the first internal terminal pad and the second internal terminal pad. 
     
     
       70. The semiconductor device of claim 64, wherein the internal terminal interconnection does not encircle the first and second internal terminal pads. 
     
     
       71. The semiconductor device of claim 64, wherein the first and second internal terminal pads are electrically insulated from the first power pad, the first ground pad and the first signal pad. 
     
     
       72. The semiconductor device of claim 64, wherein the internal terminal interconnection does not have any shielding lines extending in parallel with the internal terminal interconnection.