USRE46773EActiveUtilityPatentIndex 61
Semiconductor device and method for manufacturing the same
Est. expirySep 15, 2029(~3.2 yrs left)· nominal 20-yr term from priority
H10W 10/021H10W 10/20H01L 21/764H01L 29/66689H01L 21/823814H01L 29/7835H01L 21/823892H01L 21/823878H01L 21/82385H01L 27/0922H01L 21/823857H01L 27/11526H01L 29/7816H01L 29/1087H01L 29/0653H01L 29/4933H01L 29/0649H01L 29/0878H01L 29/1083H01L 27/11521H01L 21/823807H01L 29/456H10D 62/378H10D 84/856H10D 84/0109H10D 84/0181H10D 84/0167H10D 84/0179H10D 84/017H10D 84/0188H10D 84/0191H10D 64/663H10D 64/62H10D 62/371H10D 62/157H10D 62/116H10D 62/83H10D 30/603H10D 30/0285H10D 30/65H10D 84/038H10D 62/115H10B 41/30H10B 41/40
61
PatentIndex Score
1
Cited by
31
References
16
Claims
Abstract
A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1. A semiconductor device comprising:
a semiconductor substrate having a trench in a main surface thereof, the semiconductor substrate having a first conductivity type which is one of an n-type and a p-type;
a device being formed over the main surface of the semiconductor substrate; and
an insulating film being formed over the device and in the trench so as to cover the device and form an air-gap space in the trench, wherein
a side surface of the trench on a same level of a bottom of the air-gap space directly contacts reaches into the semiconductor substrate,
the semiconductor substrate includes a buried layer having a second conductivity type which is the other one of the n-type and the p-type, and
the trench penetrates the buried layer.
2. A semiconductor device according to claim 1 wherein,
the device has a conductive portion, and
the insulating film has a hole which reaches the conductive portion.
3. A semiconductor device according to claim 1 , wherein the trench is formed so as to surround the device entirely when seen in a plan view.
4. A semiconductor device comprising:
a semiconductor substrate having a trench in a main surface thereof, the semiconductor substrate having a first conductivity type which is one of an n-type and a p-type; a conductive portion formed over the main surface of the semiconductor substrate; and an insulating film formed over the conductive portion and in the trench to cover the conductive portion and form an air-gap in the trench, wherein a bottom of the air-gap reaches into the semiconductor substrate, the semiconductor substrate includes a buried layer having a second conductivity type which is the other one of the n-type and the p-type, and the trench penetrates the buried layer.
5. The semiconductor device according to claim 4 wherein, the insulating film has a hole which reaches the conductive portion.
6. The semiconductor device according to claim 4, wherein the trench surrounds the conductive portion entirely when seen in a plan view.
7. A semiconductor device comprising:
a first semiconductor layer having a first conductivity type which is one of an n-type and a p-type; a second semiconductor layer, on the first semiconductor layer, having a second conductivity type which is the other one of the n-type and the p-type; a third semiconductor layer, on the second semiconductor, having the first conductivity type which is the one of the n-type and the p-type; a MOS transistor having a gate electrode over the third semiconductor layer, and source and drain regions in the third semiconductor layer; a first isolation region having a first trench penetrating the third semiconductor layer and the second semiconductor layer to reach inside the first semiconductor layer, the first trench surrounding the MOS transistor; a first insulating film covering the gate electrode and filling in the first trench, while leaving an air-gap in the first trench, and a bottom of the air-gap reaches into one of the first to third semiconductor layers.
8. The semiconductor device according to claim 7, further comprising a second isolation region having a second trench disposed in the third semiconductor layer, the second trench being filled with a second insulating film, the second isolation region contacting the source or drain region in the third semiconductor layer, wherein
the second trench is shallower than the first trench.
9. The semiconductor device according to claim 8, wherein the first trench surrounds the second isolation region and the MOS transistor.
10. The semiconductor device according to claim 9, wherein the bottom of the air-gap is located in the first semiconductor layer.
11. The semiconductor device according to claim 10, wherein the air-gap extends from the third semiconductor layer to the first semiconductor layer.
12. The semiconductor device according to claim 11, wherein the first semiconductor layer includes a semiconductor substrate and an epitaxial region formed on the semiconductor substrate.
13. The semiconductor device according to claim 9, further comprising:
an interconnecting layer on the first insulating film; and a conductive layer, in the first insulating film, connecting the interconnecting layer and one of the source region and the drain region of the MOS transistor.
14. The semiconductor device according to claim 8, further comprising a third insulating film between the first insulating film and the gate electrode.
15. The semiconductor device according to claim 14, wherein
the first insulating film is a silicon oxide film, and the third insulating film is a silicon nitride film.
16. The semiconductor device according to claim 9, further comprising another second isolation region having another second trench disposed in the third semiconductor layer, the another second trench being filled with the second insulating film, the another second trench is shallower than the first trench, wherein
the first trench penetrates the second insulating film in the another second trench.Cited by (0)
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