Semiconductor device with alternating conductivity type layers having different vertical impurity concentration profiles

Abstract

A power semiconductor device is disclosed, which comprises a semiconductor layer including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type, which are periodically formed in the lateral direction, and a power semiconductor element including the semiconductor layers that are formed periodically, wherein a distribution of an amount of an impurity in a vertical direction of the first semiconductor layer differs from a distribution of an amount of an impurity in the vertical direction of the second semiconductor layer.

What is claimed is: 
     
       1. A power semiconductor device comprising:
 a first semiconductor layer of a first conductivity type; 
 a first main electrode electrically connected to the first semiconductor layer; 
 second semiconductor layers of a second conductivity type formed within the first semiconductor layer and periodically arranged in a lateral direction, a profile of an amount of an impurity in a vertical direction of the second semiconductor layers being differ different from a profile of an amount of the impurity in the vertical direction of the first semiconductor layer; 
 a third semiconductor layer of the second conductivity type selectively formed in surfaces of the first semiconductor layer and the second semiconductor layer; 
 a fourth semiconductor layer of the first conductivity type selectively formed in a surface of the third semiconductor layer; 
 a second main electrode formed to be connected to the surface of the third semiconductor layer and a surface of the fourth semiconductor layer; and 
 a control electrode formed on the first semiconductor layer, the third semiconductor layer and the fourth semiconductor layer with a gate insulating film interposed therebetween, 
 wherein the first semiconductor layer has a constant concentration of the impurity in a vertical direction from the second main electrode to the first main electrode; and 
 theeach second semiconductor layer has a concentration of the impurity distributed such that the impurity concentration is decreased in the vertical direction from the second main electrode to the first main electrode; and 
 a ratio Nt/Nb of an amount Nt of the impurity on a side of an end of each second semiconductor layer that is close to the second main electrode to an amount Nb of the impurity on a side of another end of each second semiconductor layer that is close to the first main electrode is not larger than 1.7. 
 
     
     
       2. A power semiconductor device according to  claim 1 , wherein a ratio Nt/Nb of an amount Nt of the impurity on a side of an end of the second semiconductor layer close to the second main electrode to an amount Nb of the impurity on a side of another end close to the first main electrode is not larger than 1.7. 
     
     
       3. A power semiconductor device according to claim  2  1, wherein a the ratio Nt/Nb of an amount Nt of the impurity on a side of an end of the second semiconductor layer close to the second main electrode to an amount Nb of the impurity on a side of another end close to the first main electrode is not larger is not smaller than 1.4. 
     
     
       4. A power semiconductor device according to claim 1, wherein a portion of the first semiconductor layer is provided between the first main electrode and the second semiconductor layers along the vertical direction.  
     
     
       5. A power semiconductor device according to claim 1, wherein an impurity concentration of the first semiconductor layer is uniform in a vertical direction from the second main electrode to the first main electrode.  
     
     
       6. A power semiconductor device according to claim 1, wherein the second semiconductor layers are provided in trenches, and the trenches are provided in the first semiconductor layer.  
     
     
       7. A power semiconductor device according to claim 6, wherein the impurity concentration of the first semiconductor layer is uniform.  
     
     
       8. A power semiconductor device according to claim 7, wherein the impurity concentration of the first semiconductor layer is uniform in a vertical direction from a bottom of the third semiconductor layer to a bottom of the trench.  
     
     
       9. A power semiconductor device according to claim 1, wherein the first semiconductor layer further comprises:
 a fifth semiconductor layer of the first conductivity type between the second semiconductor layers;   and a sixth semiconductor layer of the first conductivity type provided on the first electrode, wherein   an impurity concentration of the fifth semiconductor layer is lower than that of the sixth semiconductor layer.    
     
     
       10. A power semiconductor device according to claim 1, wherein the second semiconductor layers further comprise a plurality of impurity regions, each impurity region being formed by an application of an impurity at different vertical depths and having an impurity concentration, the impurity concentrations of the impurity regions substantially decreasing in a direction from the second main electrode to the first main electrode.  
     
     
       11. A power semiconductor device according to claim 10, wherein an impurity concentration of the first semiconductor layer is uniform.  
     
     
       12. A power semiconductor device according to claim 11, wherein the impurity concentration of the first semiconductor layer is uniform in a vertical direction from an impurity peak position of a top impurity region in the plurality of impurity regions to an impurity peak position of a bottom impurity region in the plurality of impurity regions.  
     
     
       13. A power semiconductor device according to claim 10, wherein a portion of the first semiconductor layer is provided between the first main electrode and the second semiconductor layers.  
     
     
       14. A power semiconductor device according to claim 10, wherein the first semiconductor layer further comprises:
 a fifth semiconductor layer of the first conductivity type between the second semiconductor layers;   and a sixth semiconductor layer of the first conductivity type provided on the first electrode, wherein   an impurity concentration of the fifth semiconductor layer is lower than that of the sixth semiconductor layer.    
     
     
       15. A power semiconductor device according to claim 10, wherein the impurity concentration of a portion of a first impurity region in the plurality of impurity regions that is closer to the second main electrode is less than the impurity concentration of a portion of a second impurity region in the plurality of impurity regions that is located closer to the first main electrode than is the first impurity region in the plurality of impurity regions.  
     
     
       16. A power semiconductor device of claim 1, wherein
 the first main electrode extends in a first direction; and   the second semiconductor layers are periodically spaced apart in the first direction.    
     
     
       17. A power semiconductor device of claim 16, wherein the second semiconductor layers comprise a plurality of columns extending inwardly of the first semiconductor layer in a second direction generally perpendicular to the first direction.  
     
     
       18. A power semiconductor device according to claim 10, wherein a ratio Nt/Nb of a maximum amount Nt of the impurity of the second semiconductor layers in the impurity region closest to the second main electrode to a maximum amount Nb of the impurity of the second semiconductor layers in the impurity region closest to the first main electrode is not larger than 1.7.  
     
     
       19. A power semiconductor device according to claim 18, wherein the ratio Nt/Nb is not smaller than 1.4.  
     
     
       20. A power semiconductor device comprising:
 a first semiconductor layer of a first conductivity type;   a first main electrode electrically connected to the first semiconductor layer;   second semiconductor layers of a second conductivity type, each second semiconductor layer formed in a substantially vertical column within the first semiconductor layer and periodically arranged in a horizontal direction;   a third semiconductor layer of the second conductivity type selectively formed in surfaces of the first semiconductor layer and the second semiconductor layer;   a fourth semiconductor layer of the first conductivity type selectively formed in a surface of the third semiconductor layer;   a second main electrode electrically connected to a surface of the third semiconductor layer and a surface of the fourth semiconductor layer;   an insulating film formed on a portion of the first semiconductor layer, a portion of the third semiconductor layer, and a portion of the fourth semiconductor layer; and   a gate electrode formed on the insulating film;   wherein an impurity concentration of the first semiconductor layer is constant in a vertical direction from the second main electrode to the first main electrode; and   wherein an impurity concentration of the second semiconductor layers decreases in a vertical direction from the second main electrode to the first main electrode, and said impurity concentration of the second semiconductor layers being different from an impurity concentration of the first semiconductor layer.    
     
     
       21. A power semiconductor device according to claim 20, wherein a ratio Nt/Nb of an amount Nt of the impurity on a side of an end of the second semiconductor layers close to the second main electrode to an amount Nb of the impurity on a side of another end of the second semiconductor layers close to the first main electrode is not larger than 1.7.  
     
     
       22. A power semiconductor device according to claim 21, wherein the ratio Nt/Nb is not smaller than 1.4.  
     
     
       23. A power semiconductor device according to claim 20, wherein the second semiconductor layers further comprise a plurality of impurity regions, each impurity region being formed by an application of an implant dosage of an impurity at different vertical depths and having an impurity concentration, the impurity concentrations of the plurality of impurity regions substantially decreasing in a direction from the second main electrode to the first main electrode.  
     
     
       24. A power semiconductor device according to claim 23, wherein a ratio Nt/Nb of a maximum amount Nt of the impurity of the second semiconductor layers in the impurity region closest to the second main electrode to a maximum amount Nb of the impurity of the second semiconductor layers in the impurity region closest to the first main electrode is not larger than 1.7.  
     
     
       25. A power semiconductor device according to claim 24, wherein the ratio Nt/Nb is not smaller than 1.4.  
     
     
       26. A power semiconductor device according to claim 23, wherein a ratio Nt/Nb of an average amount Nt of the impurity of the second semiconductor layers in the impurity region closest to the second main electrode to an average amount Nb of the impurity of the second semiconductor layers in the impurity region closest to the first main electrode is not larger than 1.7.  
     
     
       27. A power semiconductor device according to claim 26, wherein the ratio Nt/Nb is not smaller than 1.4.  
     
     
       28. A power semiconductor device according to claim 20, wherein
 an impurity concentration of a first conductivity type impurity in the first semiconductor layer is constant in a direction orthogonal to a surface of the first semiconductor layer; and   an impurity concentration of a first conductivity type impurity in the second semiconductor layers is constant in a direction from the second main electrode to the first main electrode, and an impurity concentration of a second conductivity type impurity decreases in a direction from the second main electrode to the first main electrode.    
     
     
       29. A power semiconductor device comprising:
 a first semiconductor layer of a first conductivity type;   a first main electrode electrically connected to the first semiconductor layer;   second semiconductor layers of a second conductivity type, each second semiconductor layer formed in a substantially vertical column within the first semiconductor layer and periodically arranged in a horizontal direction;   a third semiconductor layer of the second conductivity type selectively formed in surfaces of the first semiconductor layer and the second semiconductor layer;   a fourth semiconductor layer of the first conductivity type selectively formed in a surface of the third semiconductor layer;   a second main electrode electrically connected to a surface of the third semiconductor layer and a surface of the fourth semiconductor layer;   an insulating film formed on a portion of the first semiconductor layer, a portion of the third semiconductor layer, and a portion of the fourth semiconductor layer; and   a gate electrode formed on the insulating film; wherein   an impurity concentration of a first conductivity type impurity in the first semiconductor layer is constant in a direction orthogonal to a surface of the first semiconductor layer; and   an impurity concentration of a first conductivity type impurity in the second semiconductor layers is constant in a direction from the second main electrode to the first main electrode, and an impurity concentration of a second conductivity type impurity decreases in a direction from the second main electrode to the first main electrode.    
     
     
       30. A power semiconductor device according to claim 29, wherein a ratio Nt/Nb of an amount Nt of the second conductivity type impurity on a side of an end of the second semiconductor layers close to the second main electrode to an amount Nb of the second conductivity type impurity on a side of another end of the second semiconductor layers close to the first main electrode is not larger than 1.7.  
     
     
       31. A power semiconductor device according to claim 30, wherein the ratio Nt/Nb is not smaller than 1.4.  
     
     
       32. A power semiconductor device according to claim 29, wherein the second semiconductor layers further comprise a plurality of implantation regions, each implantation region being formed by the application of an ion implantation dosage at different vertical depths and having an impurity concentration substantially proportional to the ion implantation dosage, the ion implantation dosages decreasing in a direction from the second main electrode to the first main electrode.  
     
     
       33. A power semiconductor device according to claim 32, wherein a ratio Nt/Nb of a maximum amount Nt of the second conductivity type impurity of the second semiconductor layer in the implantation region closest to the second main electrode to a maximum amount Nb of the second conductivity type impurity of the second semiconductor layer in the implantation region closest to the first main electrode is not smaller than 1.4.  
     
     
       34. A power semiconductor device according to claim 29, wherein a ratio Nt/Nb of an average amount Nt of the second conductivity type impurity of the second semiconductor layers in the implantation region closest to the second main electrode to an average amount Nb of the second conductivity type impurity of the second semiconductor layer in the implantation region closest to the first main electrode is not larger than 1.7.  
     
     
       35. A power semiconductor device according to claim 34, wherein the ratio Nt/Nb is not smaller than 1.4.