Drop recipe creating method, database creating method and medium

Abstract

According to one embodiment, a plurality of test drop recipes are first created based on design data on a semiconductor integrated circuit. Based on a defect inspection result of a pattern of a hardening resin material, which is formed by pressing a template on which patterns of the semiconductor integrated circuit are formed onto the hardening resin material applied to a substrate to be processed by use of the test drop recipes, a drop recipe with least defects is selected per press position on the substrate to be processed from the test drop recipes. The selected drop recipes for respective press positions are collected per functional circuit block configuring the semiconductor integrated circuit, thereby to generate a drop recipe creation assistant database.

What is claimed is: 
     
       1. A drop recipe creating method comprising:
 storing, by a memory, a database holding first drop recipes for respective functional circuit blocks at respective imprint positions; 
 extracting, by a processor, arrangement positions of a plurality of functional circuit blocks configuring a semiconductor integrated circuit on the semiconductor integrated circuit from design data of the semiconductor integrated circuit stored in the memory; 
 extracting, by the processor, the first drop recipes for each of the functional circuit blocks configuring the semiconductor integrated circuit at designated imprint positions from the database; 
 creating, by the processor, a second drop recipe of the semiconductor integrated circuit by arranging the extracted first drop recipes based on the extracted corresponding arrangement positions and combining the arranged first drop recipes; and 
 outputting, by the processor, the second drop recipe to the memory. 
 
     
     
       2. The drop recipe creating method according to  claim 1 , comprising:
 extracting, by the processor, arrangement directions of the functional circuit blocks configuring the semiconductor integrated circuit from the design data; and 
 when creating the second drop recipe, arranging, by the processor, the extracted first drop recipes of the functional circuit blocks based on the extracted arrangement positions and arrangement directions. 
 
     
     
       3. The drop recipe creating method according to  claim 1 , further comprising
 correcting, by the processor, the discharge amount of a hardening resin material in the second drop recipe based on a representative line width of the semiconductor integrated circuit. 
 
     
     
       4. A drop recipe creating method used in transferring a pattern to a semiconductor wafer, wherein a drop recipe defines one or more application amount distributions of one or more resist materials on a semiconductor wafer, the method comprising:
 storing, in a memory, a database of first drop recipes, wherein the first drop recipes are each associated with one or more first patterns and with one or more imprint positions;   extracting, by a processor, arrangement positions on the semiconductor wafer of second patterns, the second patterns configuring patterns to be formed on the semiconductor wafer;   extracting from the database, by the processor, at least two of the first drop recipes for at least two of the second patterns at designated imprint positions on the semiconductor wafer;   arranging, by the processor, the extracted first drop recipes on the semiconductor wafer based on the extracted arrangement positions;   creating, by the processor, a second drop recipe based on the arranged first drop recipes; and   outputting, by the processor, the second drop recipe to the memory.    
     
     
       5. The drop recipe creating method according to claim 4, further comprising:
 extracting, by the processor, arrangement directions of the second patterns based on the design data;   wherein the extracted first drop recipes are also arranged based on the extracted arrangement directions.    
     
     
       6. The drop recipe creating method according to claim 4, further comprising:
 determining, by the processor, one or more discharge amounts of the one or more resist materials based on a representative pattern width of the patterns to be formed on the semiconductor wafer.    
     
     
       7. The drop recipe creating method according to claim 4, wherein the one or more application distribution amounts defined by the first drop recipes are related to at least one of a defect inspection result and a critical dimension measurement result of resist patterns created using a set of drop recipes including the first drop recipes.  
     
     
       8. The drop recipe creating method according to claim 4, wherein the one or more application distribution amounts defined by at least one of the first drop recipes are related to one or more features of the resist materials.  
     
     
       9. The drop recipe creating method according to claim 8, wherein the one or more features include at least one of contraction rate, elastic force, base material adhesion force, charging property, solvent resistance, and fluorine content rate.  
     
     
       10. The drop recipe creating method according to claim 4, wherein the one or more application distribution amounts defined by at least one of the first drop recipes are related to a flowing direction of at least one of the resist materials in the associated first patterns.  
     
     
       11. The drop recipe creating method according to claim 4, wherein at least some of the first patterns are associated with one or more circuit blocks.  
     
     
       12. The drop recipe creating method according to claim 11, wherein the one or more circuit blocks include at least one functional circuit block.  
     
     
       13. The drop recipe creating method according to claim 11, wherein the one or more circuit blocks include at least one test circuit block.  
     
     
       14. The drop recipe creating method according to claim 11, wherein the one or more circuit blocks include at least one peripheral circuit block.  
     
     
       15. The drop recipe creation method according to claim 4, wherein at least one of the first patterns includes one or more cell patterns.  
     
     
       16. The drop recipe creation method according to claim 4, wherein at least one of the first patterns includes one or more lines.  
     
     
       17. The drop recipe creation method according to claim 4, wherein one of the first recipes is associated with one of the first patterns to be formed on a first shot area of the semiconductor wafer and one of the first recipes is associated with one of the first patterns to be formed on a second shot area of the semiconductor wafer, wherein the first shot area of the semiconductor wafer does not include a periphery of the semiconductor wafer and the second shot area of the semiconductor wafer includes the periphery of the semiconductor wafer.  
     
     
       18. The drop recipe creation method according to claim 17, wherein both of the first patterns to be formed on the first and the second shot areas of the semiconductor wafer include cell patterns.  
     
     
       19. The drop recipe creation method according to claim 4, wherein the extracted first drop recipes are respectively associated with the first patterns in the database corresponding to the second patterns of which arrangement positions are extracted.  
     
     
       20. A non-transitory computer readable medium comprising instructions that, when executed by a computer, cause the computer to perform a method of creating a drop recipe that defines one or more application distribution amounts of one or more resist materials on a semiconductor wafer, the method being used in transferring a pattern to a semiconductor wafer and comprising:
 storing, in a memory, a database including first drop recipes, wherein the first drop recipes are associated with one or more first patterns and with one or more imprint positions;   extracting arrangement positions on the semiconductor wafer of second patterns, the second patterns configuring patterns to be formed on the semiconductor wafer;   extracting from the database at least two of the first drop recipes for at least two of the second patterns at designated imprint positions;   arranging the extracted first drop recipes based on the extracted arrangement positions;   creating a second drop recipe based on the arranged first drop recipes; and   outputting the second drop recipe to the memory.    
     
     
       21. The medium according to claim 20, wherein the method further comprises:
 extracting arrangement directions of the second patterns based on the design data;   wherein the extracted first drop recipes are also arranged based on the extracted arrangement directions.    
     
     
       22. The medium according to claim 20, wherein the method further comprises:
 determining one or more discharge amounts of the resist materials based on a representative pattern width of the patterns to be formed on the semiconductor wafer.    
     
     
       23. The medium according to claim 20, wherein the one or more application amount distributions defined by the first drop recipes are related to at least one of a defect inspection result and a critical dimension measurement result of resist patterns created using a set of drop recipes including the first drop recipes.  
     
     
       24. The medium according to claim 20, wherein the one or more application amount distributions defined by at least one of the first drop recipes are related to one or more features of the resist materials.  
     
     
       25. The medium according to claim 24, wherein the one or more features include at least one of contraction rate, elastic force, base material adhesion force, charging property, solvent resistance, and fluorine content rate.  
     
     
       26. The medium according to claim 20, wherein the one or more application amount distributions defined by at least one of the first drop recipes are related to a flowing direction of at least one of the resist materials in the associated first patterns.  
     
     
       27. The medium according to claim 20, wherein at least some of the first patterns are associated with one or more circuit blocks.  
     
     
       28. The medium according to claim 27, wherein the one or more circuit blocks include at least one functional circuit block.  
     
     
       29. The medium according to claim 27, wherein the one or more circuit blocks include at least one test circuit block.  
     
     
       30. The medium according to claim 27, wherein the one or more circuit blocks include at least one peripheral circuit block.  
     
     
       31. The medium according to claim 20, wherein at least one of the first patterns includes one or more cell patterns.  
     
     
       32. The medium according to claim 20, wherein at least one of the first patterns includes one or more lines.  
     
     
       33. The medium according to claim 20, wherein one of the first recipes is associated with one of the first patterns to be formed on a first shot area of the semiconductor wafer and one of the first recipes is associated with one of the first patterns to be formed on a second shot area of the semiconductor wafer, wherein the first shot area of the semiconductor wafer does not include a periphery of the semiconductor wafer and the second shot area of the semiconductor wafer includes the periphery of the semiconductor wafer.  
     
     
       34. The medium according to claim 33, wherein both of the first patterns to be formed on the first and the second shot areas of the semiconductor wafer include cell patterns.  
     
     
       35. The medium according to claim 20, wherein the extracted first drop recipes are respectively associated with the first patterns in the database corresponding to the second patterns of which arrangement positions are extracted.