Diode-less array for one-time programmable memory

Abstract

A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.

What is claimed is: 
     
       1. A memory array structure, comprising:
 a word line; 
 a column conductor connected with the word line and having a vertical sidewall extending through a plurality of elevations; 
 a dielectric material on at least a portion of the vertical sidewall of the column conductor; 
 a plurality of bit lines disposed at the plurality of elevations; and 
 a plurality of memory units, defined at intersections of the vertical sidewall of the column conductor and the bit lines, a plurality of fuse links, each of which is includes a fuse link coupled between the dielectric material on the vertical sidewall of the column conductor and one of the bit lines, 
 wherein the dielectric material is continuous between the intersections. 
 
     
     
       2. The memory array structure of  claim 1 , wherein a memory element of each memory unit is a fuse. 
     
     
       3. The memory array structure of  claim 1 , wherein the plurality of fuse links is formed of in the plurality of memory units comprise doped or undoped polysilicon. 
     
     
       4. The memory array structure of  claim 1 , further comprising:
 an insulator filling voids between the bit lines, the fuse links and the vertical sidewall of the column conductor. 
 
     
     
       5. The memory array structure of  claim 1 , wherein a selected fuse link coupled between the dielectric material on the column conductor and a selected bit line in a selected memory unit is blown by applying a programming voltage on the word line and grounding the selected bit line. 
     
     
       6. The memory array structure of  claim 1 , wherein a selected fuse link coupled between the dielectric material on the column conductor and a selected bit line in a selected memory unit is measured by applying a negative read voltage on the word line and applying a positive read voltage on the selected bit line. 
     
     
       7. The memory array structure of  claim 1 , wherein the dielectric material is one of nitride and silicon dioxide. 
     
     
       8. The memory array structure of  claim 1 , wherein the word line, the bit lines and the column conductor are formed of at least one of polysilicon, copper, aluminum, germanium, tantalum, silver, gold, nickel, chromium, tin, tungsten, zinc, titanium and indium. 
     
     
       9. A memory array structure, comprising:
 a plurality of first row conductors, extending in a first row direction and disposed at a plurality of elevations; 
 a column conductor, having a vertical sidewall extending in a column direction through the plurality of elevations, and being adjacent to the plurality of first row conductors; 
 a dielectric material on at least a portion of the vertical sidewall of the column conductor; and 
 a plurality of memory units, defined at intersections of the vertical sidewall of the column conductor and the first row conductors, a plurality of fuse links, each of which is the plurality of memory units includes a fuse link coupled between the dielectric material on the vertical sidewall of the column conductor and one of the first row conductors, 
 wherein the dielectric material is continuous between the intersections. 
 
     
     
       10. The memory array structure of  claim 9 , further comprising:
 a second row conductor, extending in a second row direction, disposed at a different elevation other than the plurality of elevations, and connected with the vertical sidewall of the column conductor. 
 
     
     
       11. The memory array structure of  claim 10 , wherein first row conductors form bit lines and the second row conductor forms a word line. 
     
     
       12. The memory array structure of  claim 9 , wherein a memory element of each memory unit is a fuse. 
     
     
       13. The memory array structure of  claim 9 , wherein the plurality of fuse links link in at least one of the memory units is formed of doped or undoped polysilicon. 
     
     
       14. The memory array structure of  claim 9 , further comprising:
 an insulator filling voids between the first row conductors, the fuse links and the vertical sidewall of the column conductor. 
 
     
     
       15. The memory array structure of  claim 9 , wherein a selected fuse link is blown by transmitting a programming voltage to the column conductor and grounding a selected first row conductor. 
     
     
       16. The memory array structure of  claim 9 , wherein a selected fuse link is measured by transmitting a negative read voltage to the column conductor and applying a positive read voltage on a selected first row conductor. 
     
     
       17. The memory array structure of  claim 9 , wherein the dielectric material is one of nitride and silicon dioxide. 
     
     
       18. The memory array structure of  claim 9 , wherein the first row conductors and the column conductor are formed of at least one of polysilicon, copper, aluminum, germanium, tantalum, silver, gold, nickel, chromium, tin, tungsten, zinc, titanium and indium. 
     
     
       19. A memory device comprising:
 a 3D memory array including:
 a first conductor extending in a vertical direction and a plurality of second conductors extending in a horizontal direction and having vertical sides, wherein the first conductor has a vertical sidewall disposed adjacent to the vertical sides of the plurality of second conductors, and the plurality of second conductors is disposed at different elevations along the vertical sidewall of the first conductor; and 
 a plurality of data storage elements located between the vertical sidewall of first conductor and the vertical sides of the plurality of second conductors. 
   
     
     
       20. The memory device of claim 19, wherein a second dielectric layer is on at least a portion of the vertical sidewall of the first conductor, the second dielectric layer is continuous between parts of the second dielectric layer through adjacent data storage elements of the plurality of data storage elements. 
     
     
       21. The memory device of claim 20, wherein the adjacent data storage elements are positioned on adjacent different ones of the different elevations. 
     
     
       22. The memory device of claim 19, comprising:
 a periphery circuit region; and   a first dielectric layer over the periphery circuit region,   wherein the 3D memory array is over the first dielectric layer.   
     
     
       23. A memory device comprising:
 a first plurality of conductors extending vertically and arranged in a spaced apart relationship along a second direction;   a second plurality of conductors, wherein the first plurality of conductors are disposed adjacent to the second plurality of conductors, and conductors of the second plurality of conductors are disposed at different elevations along adjacent conductors in the first plurality of conductors;   a first dielectric layer on at least a portion of a vertical sidewall of a first conductor of the first plurality of conductors;   a second dielectric layer on at least a portion of a vertical sidewall of a second conductor of the first plurality of conductors;   a first plurality of data storage elements located between the first dielectric layer and sides of the conductors in the second plurality of conductors facing the vertical sidewalls of the first conductor;   a second plurality of data storage elements located between the second dielectric layer and sides of conductors in the second plurality of conductors facing the vertical sidewalls of the second conductor, wherein one of the first data storage elements can be selected by the first conductor of the first plurality of conductors and a first conductor of the second plurality of conductors, and one of the second data storage elements can be selected by the second conductor of the first plurality of conductors and the first conductor of the second plurality of conductors.   
     
     
       24. The memory device of claim 23, wherein the first dielectric layer is continuous between parts of the dielectric layer through adjacent data storage elements of the plurality of data storage elements. 
     
     
       25. The memory device of claim 24, wherein the adjacent data storage elements are positioned on adjacent different ones of the different elevations. 
     
     
       26. The memory device of claim 23, wherein a periphery circuit region is under the first plurality of conductors, the second plurality of conductors, the first plurality of data storage elements and the second plurality of data storage elements. 
     
     
       27. A memory device comprising:
 a first plurality of conductors extending vertically and arranged in a spaced apart relationship along a second direction, the conductors in the first plurality of conductors having vertical sidewalls;   a second plurality of conductors and having sides facing the vertical sidewalls of conductors in the first plurality of conductors, wherein the vertical sidewalls of conductors in the first plurality of conductors are disposed adjacent to the sides of conductors in the second plurality of conductors, conductors of the second plurality of conductors disposed at different elevations along adjacent conductors in the first plurality of conductors, the first and second directions are different;   a dielectric layer on at least portions of the vertical sidewalls of conductors in the first plurality of conductors; and   a plurality of data storage elements located between the portions of the vertical sidewalls of conductors in the first plurality of conductors and the sides of conductors in the second plurality of conductors, wherein a first data storage element of the data storage elements can be selected by a first conductor of the first plurality of conductors and a first conductor of the second plurality of conductors, and a second data storage element of the data storage elements can be selected by a second conductor of the first plurality of conductors and the first conductor of the second plurality of conductors, the first and second data storage elements are arranged in the second direction.   
     
     
       28. The memory device of claim 27, wherein plural data storage elements of the plurality of data storage elements are located between the dielectric layer and the sides of conductors in the second plurality of conductors. 
     
     
       29. The memory device of claim 28, wherein the dielectric layer is continuous between parts of the dielectric layer through adjacent data storage elements of the plurality of data storage elements. 
     
     
       30. The memory device of claim 29, wherein the adjacent data storage elements are positioned on adjacent different ones of the different elevations. 
     
     
       31. The memory device of claim 30, wherein a periphery circuit region is under the first plurality of conductors, the second plurality of conductors and the plurality of data storage elements.