Flash memory devices having three dimensional stack structures and methods of driving same

Abstract

Flash memory devices are provided including a plurality of layers stacked vertically. Each of the plurality of layers include a plurality of memory cells. A row decoder is electrically coupled to the plurality of layers and configured to supply a wordline voltage to the plurality of layers. Memory cells provided in at least two layers of the plurality of layers belong to a same memory block and wordlines associated with the memory cells in the at least two layers of the plurality of layers are electrically coupled.

That which is claimed is: 
     
       1. A flash memory device having a three dimensional (3D) stack structure, the flash memory device comprising:
 a memory array having a 3D structure and including memory cells arranged in a plurality of layers stacked vertically, one layer of the plurality of layers includes memory cells of a first and second directions, and another layer of the plurality of layers includes memory cells of a third direction substantially perpendicular to the first and second directions; and 
 a row decoder electrically coupled to the plurality of layers and configured to supply a wordline voltage to the plurality of layers, 
 wherein memory cells in at least two layers of the plurality of layers belong to a same memory block and wherein wordlines associated with the memory cells in the at least two layers of the plurality of layers are electrically coupled. 
 
     
     
       2. The device of  claim 1 , wherein the wordlines associated with the memory cells in the same memory block are driven using a same row decoder. 
     
     
       3. The device of  claim 1 :
 wherein the plurality of layers comprises a first layer and a second layer; and 
 wherein a first cell region of the memory cells in the first layer and a second cell region of the memory cells in the second layer are included in the same memory block. 
 
     
     
       4. The device of  claim 3 :
 wherein wordlines associated with the first cell region and wordlines associated with the second cell region are electrically coupled; and 
 wherein the row decoder is configured to supply a same wordline voltage to the electrically coupled wordlines. 
 
     
     
       5. The device of  claim 1 , wherein the device is NAND flash memory. 
     
     
       6. The device of  claim 1 , wherein the first and second directions are respectively X and Y-directions rectangular to each other of the 3D structure, and the third direction is Z-direction substantially perpendicular to the X and Y-directions of the 3D structure. 
     
     
       7. The device of  claim 1 , wherein an erase operation of the flash memory device is performed in a unit of the same memory block. 
     
     
       8. A flash memory device comprising:
 a plurality of layers stacked vertically, each of the plurality of layers including a plurality of memory cells; and   a row decoder electrically coupled to the plurality of layers and configured to supply a wordline voltage to the plurality of layers;   wherein memory cells in at least two layers of the plurality of layers belong to a same memory block and wherein wordlines associated with the memory cells in the at least two layers of the plurality of layers are electrically coupled;   wherein the same memory block comprises a plurality of first cell strings in the first layer and a plurality of second cell strings in the second layer;   wherein each of the first cell strings comprises a plurality of first memory cells connected in series and a first string selection transistor and a first ground selection transistor connected to the first memory cells; and   wherein each of the second cell strings comprises a plurality of second memory cells connected in series and a second string selection transistor and a second ground selection transistor connected to the second memory cells.   
     
     
       9. The device of  claim 8 , wherein each of the first cell strings and the second cell strings is connected to the same bitline, and one end of each of the first string selection transistor and the second string selection transistor is connected to the bitline, and one end of each of the first ground selection transistor and the second ground selection transistor is connected to a common source line. 
     
     
       10. The device of  claim 9 , wherein, during a program operation of the device, a first voltage Vpgm used to perform a main program operation is supplied to a wordline of a selected memory cell, and a second voltage Vpass, used to perform a boosting operation, is supplied to wordlines of unselected memory cells. 
     
     
       11. The device of  claim 10 , wherein, when a first memory cell is programmed, the first string selection transistor is turned on and the second string selection transistor is turned off, and when a second memory cell is programmed, the first string selection transistor is turned off and the second string selection transistor is turned on. 
     
     
       12. The flash memory device of  claim 10 , wherein the program operation comprises a pre-charge period before a main program is performed, and during the pre-charge period, at least one of the first cell string and the second cell string is electrically connected to the bitline. 
     
     
       13. The device of  claim 9 , wherein, during a read operation of the device, when a first memory cell is read, the first string selection transistor is turned on and the second string selection transistor is turned off, and when a second memory cell is read, the first string selection transistor is turned off and the second string selection transistor is turned on. 
     
     
       14. The device of  claim 13 , wherein, when a first memory cell is read, the first ground selection transistor is turned on and the second ground selection transistor is turned off, and when a second memory cell is read, the first ground selection transistor is turned off and the second ground selection transistor is turned on. 
     
     
       15. The device of  claim 13 , wherein the read operation comprises a pre-charge period before a main read operation is performed, and during the pre-charge period, at least one of the first cell string and the second cell string is electrically connected to the bitline. 
     
     
       16. The device of  claim 9 , wherein during an erase operation of the device, the first and second string selection transistors and the first and second ground selection transistors are in a floating state, and an erase voltage Verase of high voltage is applied to a bulk of the first and second layers. 
     
     
       17. The device of  claim 16 , wherein, during an erase operation of the memory device, memory cells disposed in the first cell string and the second cell string are simultaneously erased. 
     
     
       18. The device of  claim 8 , wherein an address comprising a plurality of bits to select the memory cell is supplied to the flash memory device, and at least one bit of the plurality of bits of the address comprises information for selecting one of the plurality of layers. 
     
     
       19. The device of  claim 18 , wherein switching of the first string selection transistor disposed in the first cell string and the second string selection transistor disposed in the second cell string is controlled based on at least one bit for selecting the layers. 
     
     
       20. The device of  claim 18 , wherein switching of the first ground selection transistor disposed in the first cell string and the second ground selection transistor disposed in the second cell string is controlled based on at least one bit for selecting the layers. 
     
     
       21. A method of driving a flash memory device having a three dimensional (3D) stack structure and having at least one memory block, the flash memory device includes a memory array having a 3D structure and including memory cells arranged in a plurality of semiconductor layers stacked vertically, one layer of the plurality of semiconductor layers includes memory cells of a first and second directions, and another one layer of the plurality of semiconductor layers includes memory cells of a third direction substantially perpendicular to the first and second directions, wherein at least one first cell string disposed in a first semiconductor layer and at least one second cell string disposed in a second semiconductor layer stacked on the first semiconductor layer are set to one memory block, and each of wordlines connected to the first cell string and each of wordlines connected to the second cell string are electrically connected to one another, the method comprising:
 erasing the memory device such that memory cells of the first cell string and the second cell string in the one memory block are simultaneously erased.   
     
     
       22. The method of  claim 21 , wherein an address comprising a plurality of bits to select the memory cells is supplied to the flash memory device, and the address is encoded so that at least one bit has information for selecting the first semiconductor layer or the second semiconductor layer. 
     
     
       23. The method of  claim 22 , wherein switching of at least one of the first string selection transistor and the first ground selection transistor disposed in the first cell string and the second string selection transistor and the second ground selection transistor disposed in the second cell string is controlled based on at least one bit for selecting the semiconductor layers. 
     
     
       24. A method of driving a flash memory device having at least one memory block, wherein at least one first cell string disposed in a first semiconductor layer and at least one second cell string disposed in a second semiconductor layer stacked on the first semiconductor layer are set to one memory block, and each of wordlines connected to the first cell string and each of wordlines connected to the second cell string are electrically connected to one another, the method comprising:
 erasing the memory device such that memory cells of the first cell string and the second cell string in the one memory block are simultaneously erased,   wherein programming memory cells included in the first cell string comprises:   applying a pre-charge voltage to a bitline and connecting the first cell string and the second sell string to the bitline;   controlling a first string selection transistor to be turned on and controlling a second string selection transistor to be turned off; and   supplying a first voltage Vpgam used to perform a main program operation to a wordline of a selected memory cell and supplying a second voltage Vpass used to perform a boosting operation to wordlines of unselected memory cells.   
     
     
       25. A method of driving a flash memory device having at least one memory block, wherein at least one first cell string disposed in a first semiconductor layer and at least one second cell string disposed in a second semiconductor layer stacked on the first semiconductor layer are set to one memory block, and each of wordlines connected to the first cell string and each of wordlines connected to the second cell string are electrically connected to one another, the method comprising:
 erasing the memory device such that memory cells of the first cell string and the second cell string in the one memory block are simultaneously erased,   wherein reading memory cells included in the first cell string comprises:   applying a pre-charge voltage to a bitline and connecting the first cell string and the second cell string to the bitline;   controlling the first string selection transistor and the first ground selection transistor to be turned on and controlling the second string selection transistor and the second ground selection transistor to be turned off; and   supplying a wordline voltage to each of a selected wordline and unselected wordlines.   
     
     
       26. The method of  claim 25 , wherein during the pre-charge operation the first string selection transistor and the second string selection transistor are turned on so that the first cell string and the second cell string are connected to the bitline. 
     
     
       27. The method of  claim 25 , wherein during the pre-charge operation a pre-charge voltage is supplied to a selected bitline and unselected bitlines. 
     
     
       28. A flash memory device having a three dimensional (3D) stack structure, the flash memory device comprising:
 a memory array having a 3D structure and including a plurality of memory cells arranged in a plurality of layers that are vertically stacked and include a first layer and a second layer, the first layer including, among the plurality of memory cells, a first group of memory cells disposed at first and second directions, the second layer including a second group of memory cells, among the plurality of memory cells, the second group of memory cells disposed at the first and the second directions and stacked on the first group of memory cells in a third direction that is substantially perpendicular both to the first direction and to the second direction; and   a row decoder electrically coupled to the plurality of layers and configured to supply a first wordline voltage to the plurality of layers,   wherein, among the plurality of memory cells, a third group of memory cells disposed in at least two layers among the plurality of layers belong to the same memory block,   a plurality of word-lines associated with the third group of memory cells that are included in the at least two layers of the plurality of layers are electrically coupled,   the memory array includes a first cell string and a second cell string, the first cell string including first memory cells among the plurality of memory cells and a first string selection transistor (SST) connected to a first string selection line (SSL), the second cell string including second memory cells among the plurality of memory cells and a second SST connected to a second SSL, the first cell string and the second cell string being connected to a first bit-line,   one of the first memory cells and one of the second memory cells are connected to a first word-line among the plurality of word-lines,   during a first period, a second voltage for electrically connecting the first bit-line to a first channel of the first cell string is applied to the first SSL, and a third voltage for electrically connecting the first bit-line to a second channel of the second cell string is applied to the second SSL,   during a second period that is later than the first period, a fourth voltage for electrically disconnecting the first bit-line from the second channel is applied to the second SSL, and   during a third period that is later than the second period, a program voltage is applied to the first word-line.   
     
     
       29. The flash memory device of claim 28, wherein a power supply voltage is applied to the first bit-line during the first period. 
     
     
       30. The flash memory device of claim 29, wherein a ground voltage is applied to the first bit-line during the third period. 
     
     
       31. The flash memory device of claim 28, wherein a power supply voltage is applied to the first bit-line during the first through third periods. 
     
     
       32. The flash memory device of claim 28, wherein the second voltage is equal to the third voltage. 
     
     
       33. The flash memory device of claim 32, wherein the fourth voltage is a ground voltage. 
     
     
       34. The flash memory device of claim 33, wherein the first bit-line is electrically connected to the first channel during the second period. 
     
     
       35. The flash memory device of claim 28, wherein the third group of memory cells that are included in the at least two layers of the plurality of layers are connected to the first bit-line. 
     
     
       36. The flash memory device of claim 28, wherein the third direction is substantially perpendicular to a well region of the memory array. 
     
     
       37. The flash memory device of claim 28, wherein the first cell string includes a first ground selection transistor (GST) connected to a first ground selection line (GSL),
 the second cell string includes a second GST connected to a second GSL, and   a ground voltage is applied to the first GSL and the second GSL during the first through third periods.   
     
     
       38. The flash memory device of claim 28, wherein an erase operation of the flash memory device is performed in a unit of the same memory block. 
     
     
       39. The flash memory device of claim 28, wherein an erase operation of the third group of memory cells that belong to the same memory block is performed concurrently for each of the memory cells the third group of memory cells. 
     
     
       40. The flash memory device of claim 28, wherein the first memory cells are disposed in the first layer and the second memory cells are disposed in the second layer. 
     
     
       41. A flash memory device having a three dimensional (3D) stack structure, the flash memory device comprising:
 a memory array having a 3D structure and including a plurality of memory cells arranged in a plurality of layers that are vertically stacked and include a first layer and a second layer, the first layer including, among the plurality of memory cells, a first group of memory cells disposed at first and second directions, the second layer including a second group of memory cells, among the plurality of memory cells, the second group of memory cells disposed in the first and the second directions and stacked on the first group of memory cells in a third direction that is substantially perpendicular both to the first direction and to the second direction; and   a row decoder electrically coupled to the plurality of layers and configured to supply a first wordline voltage to the plurality of layers,   wherein, among the plurality of memory cells, a third group of memory cells disposed in at least two layers among the plurality of layers belong to the same memory block,   a plurality of word-lines associated with the third group of memory cells that are included in the at least two layers of the plurality of layers are electrically coupled,   the memory array includes a first cell string, a second cell string, a third cell string and a fourth cell string, the first cell string including a first plurality of memory cells among the plurality of memory cells and a first string selection transistor (SST) connected to a first string selection line (SSL), the second cell string including a second plurality of memory cells among the plurality of memory cells and a second SST connected to a second SSL, the third cell string including a third plurality of memory cells among the plurality of memory cells and a third SST connected to the first SSL, the fourth cell string including a fourth plurality of memory cells among the plurality of memory cells and a fourth SST connected to the second SSL, the first cell string and the second cell string being connected to a first bit-line, the third cell string and the fourth cell string being connected to a second bit-line,   one of the first plurality of memory cells, one of the second plurality of memory cells, one of the third plurality of memory cells and one of the fourth plurality of memory cells are connected to a first word-line among the plurality of word-lines,   during a first period, a second voltage for electrically connecting the first bit-line to a first channel of the first cell string is applied to the first SSL, a third voltage for electrically connecting the first bit-line to a second channel of the second cell string is applied to the second SSL, and a power supply voltage is applied to the first bit-line,   during a second period that is later than the first period, a ground voltage is applied to the second SSL and the first bit-line, and   during a third period that is later than the second period, a program voltage is applied to the first word-line.   
     
     
       42. The flash memory device of claim 41, wherein the power supply voltage is applied to the second bit-line during the first through third periods. 
     
     
       43. The flash memory device of claim 42, wherein the second voltage is applied to the first SSL during the second period. 
     
     
       44. The flash memory device of claim 41, wherein the power supply voltage is applied to the second bit-line during the first through third periods. 
     
     
       45. The flash memory device of claim 41, wherein the second voltage is equal to the third voltage. 
     
     
       46. The flash memory device of claim 41, wherein the first bit-line and the first channel are electrically connected during the second period. 
     
     
       47. The flash memory device of claim 41, wherein the third group of memory cells that are included in the at least two layers of the plurality of layers are connected to the first bit-line. 
     
     
       48. The flash memory device of claim 41, wherein the third direction is substantially perpendicular to a well region of the memory array. 
     
     
       49. The flash memory device of claim 41, wherein the first cell string includes a first ground selection transistor (GST) connected to a first ground selection line (GSL),
 the second cell string includes a second GST connected to a second GSL, and   the ground voltage is applied to the first GSL and the second GSL during the first through third periods.   
     
     
       50. The flash memory device of claim 41, wherein an erase operation of the flash memory device is performed in a unit of the same memory block. 
     
     
       51. The flash memory device of claim 41, wherein an erase operation of the third group of memory cells that belong to the same memory block is performed concurrently for each memory cell in the third group of memory cells. 
     
     
       52. The flash memory device of claim 41, wherein the first plurality of memory cells are disposed in the first layer and the second plurality of memory cells are disposed in the second layer. 
     
     
       53. A flash memory device having a three dimensional (3D) stack structure, the flash memory device comprising:
 a memory array having a 3D structure and including a plurality of memory cells arranged in a plurality of layers that are vertically stacked and include a first layer and a second layer, the first layer including, among the plurality of memory cells, a first group of memory cells disposed at first and second directions, the second layer including a second group of memory cells, among the plurality of memory cells, the second group of memory cells disposed in the first and the second directions and stacked on the first group of memory cells in a third direction that is substantially perpendicular both to the first direction and to the second direction; and   a row decoder electrically coupled to the plurality of layers and configured to supply a first wordline voltage to the plurality of layers,   wherein, among the plurality of memory cells, a third group of memory cells disposed in at least two layers among the plurality of layers belong to the same memory block,   a plurality of word-lines associated with the third group of memory cells that are included in the at least two layers of the plurality of layers are electrically coupled,   the memory array includes a first cell string and a second cell string, the first cell string including a first memory cell and a second memory cell among the plurality of memory cells, the second cell string including a third memory cell and a fourth memory cell among the plurality of memory cells, the first memory cell and the third memory cell being connected to a first word-line among the plurality of word-lines, the second memory cell and the fourth memory cell being connected to a second word-line among the plurality of word-lines, the first cell string and the second cell string being connected to a first bit-line, and   each of the first memory cell and the third memory cell is programmed before the second memory cell and the fourth memory cell are programmed.   
     
     
       54. The flash memory device of claim 53, wherein the first cell string includes a first ground selection transistor (GST), a distance between the second memory cell and the first GST being greater than a distance between the first memory cell and the first GST. 
     
     
       55. The flash memory device of claim 53, wherein the third direction is substantially perpendicular to a well region of the memory array. 
     
     
       56. The flash memory device of claim 53, wherein an erase operation of the flash memory device is performed in a unit of the same memory block. 
     
     
       57. The flash memory device of claim 53, wherein an erase operation of the third group of memory cells that belong to the same memory block is performed concurrently for each of the memory cells in the third group of memory cells. 
     
     
       58. The flash memory device of claim 53, wherein the first group of memory cells are disposed in the first layer and the second group of memory cells are disposed in the second layer. 
     
     
       59. The flash memory device of claim 53, wherein the first memory cell is programmed before the third memory cell is programmed. 
     
     
       60. The flash memory device of claim 59, wherein the memory array further includes a third cell string and a fourth cell string, the third cell string including a fifth memory cell and a sixth memory cell among the plurality of memory cells, the fourth cell string including a seventh memory cell and an eighth memory cell among the plurality of memory cells, the fifth memory cell and the seventh memory cell being connected to the first word-line, the sixth memory cell and the eighth memory cell being connected to the second word-line,
 the first memory cell and fifth memory cell are programmed concurrently, and   the third memory cell and seventh memory cell are programmed concurrently.   
     
     
       61. A flash memory device having a three dimensional (3D) stack structure, the flash memory device comprising:
 a memory array having a 3D structure and including a plurality of memory cells arranged in a plurality of layers that are vertically stacked and include a first layer and a second layer, the first layer including, among the plurality of memory cells, first memory cells disposed at first and second directions, the second layer including second memory cells among the plurality of memory cells, the second memory cells disposed in the first and the second directions and stacked on the first memory cells in a third direction that is substantially perpendicular both to the first direction and to the second direction; and   a row decoder electrically coupled to the plurality of layers and configured to supply a wordline voltage to the plurality of layers,   wherein third memory cells disposed in at least two layers among the plurality of layers belong to the same memory block,   a plurality of word-lines associated with the third memory cells that are included in at least two layers of the plurality of layers are electrically coupled, and   each of the first memory cells is programmed before the second memory cells are programmed.   
     
     
       62. The flash memory device of claim 61, wherein the third direction is substantially perpendicular to a well region of the memory array. 
     
     
       63. The flash memory device of claim 61, wherein an erase operation of the flash memory device is performed in a unit of the same memory block. 
     
     
       64. The flash memory device of claim 61, wherein an erase operation of the third memory cells that belong to the same memory block is performed concurrently for each of the third memory cells. 
     
     
       65. A flash memory device having a three dimensional (3D) stack structure, the flash memory device comprising:
 a memory array having a 3D structure and including a plurality of memory cells arranged in a plurality of layers that are vertically stacked and include a first layer and a second layer, the first layer including, among the plurality of memory cells, a first group of memory cells disposed at first and second directions, the second layer including a second group of memory cells, among the plurality of memory cells, the second group of memory cells disposed in the first and the second directions and stacked on the first group of memory cells in a third direction that is substantially perpendicular both to the first direction and to the second direction; and   a row decoder electrically coupled to the plurality of layers and configured to supply a first wordline voltage to the plurality of layers,   wherein, among the plurality of memory cells, a third group of memory cells disposed in at least two layers among the plurality of layers belong to the same memory block,   a plurality of word-lines associated with the third group of memory cells that are included in the at least two layers of the plurality of layers are electrically coupled,   the memory array includes a first cell string and a second cell string, the first cell string including a first plurality of memory cells among the plurality of memory cells and a first string selection transistor (SST) connected to a first string selection line (SSL), the second cell string including a second plurality of memory cells among the plurality of memory cells and a second SST connected to a second SSL,   a first cell among the first plurality of memory cells and a second cell among the second plurality of memory cells being connected to a first word-line among the plurality of word-lines,   the first cell string and the second cell string are connected to a first bit-line,   during a first period, a second voltage to turn-on the first SST is applied to the first SSL and a precharge voltage is applied to the first bit-line,   during a second period later than the first period, a third voltage to turn-off the first SST is applied to the first SSL, and   during a third period that is later than the second period, a selected word-line read voltage is applied to the first word-line.   
     
     
       66. The flash memory device of claim 65, wherein, during the first through third periods, the second voltage is applied to the second SSL. 
     
     
       67. The flash memory device of claim 65, wherein the first cell string includes a first ground selection transistor (GST) connected to a first ground selection line (GSL), and
 during the first period, a ground voltage is applied to the first GSL.   
     
     
       68. The flash memory device of claim 65, wherein a third cell among the first plurality of memory cells and a fourth cell among the second plurality of memory cells are connected to a second word-line among the plurality of word-lines, and
 during the third period, a read-pass voltage lower than the selected word-line read voltage is applied to the second word-line.   
     
     
       69. The flash memory device of claim 68, wherein the second voltage is equal to the read-pass voltage. 
     
     
       70. The flash memory device of claim 69, wherein the third voltage is a ground voltage. 
     
     
       71. The flash memory device of claim 65, wherein the third direction is substantially perpendicular to a well region of the memory array. 
     
     
       72. The flash memory device of claim 65, wherein an erase operation of the flash memory device is performed in a unit of the same memory block. 
     
     
       73. The flash memory device of claim 65, wherein an erase operation of the third group of memory cells that belong to the same memory block is performed concurrently for each of the memory cells in the third group of memory cells.