NAND flash memory device and method of making same

Abstract

An integrated circuit includes a NAND string including a string selection transistor SST and a ground selection transistor GST disposed at either end of series-connected memory storage cells MC. Each of the memory storage cells is a memory transistor having a floating gate, and at least one of the string selection transistor SST and the ground selection transistor GST is a memory transistor having a floating gate. The threshold voltage Vth of programmable string selection transistors SST and the ground selection transistor GST is variable and user controllable and need not be established by implantation during manufacture. Each of the programmable string selection transistors SST and the ground selection transistors GST in a memory block may be used to store random data, thus increasing the memory storage capacity of the flash memory device.

What is claimed is: 
     
       1. A method of programming a flash memory device having a plurality of NAND cell units in each of a plurality of memory blocks, a plurality of memory cell transistors in each NAND cell unit controlled by respective wordlines, a first selection line connected to a first selection transistor in each of the NAND cell units in a memory block, each first selection transistor being a memory transistor connected in series to the plurality of memory cell transistors in each NAND cell unit, the method comprising:
 simultaneously erasing all of the memory cell transistors in the first memory block among the plurality of memory blocks;   programming all the memory cell transistors connected to a first wordline in the first memory block; and   programming and program-inhibiting all first selection transistors in all NAND cell units of the first memory block.   
     
     
       2. The method of  claim 1 , further comprising verifying the threshold voltage of each first selection transistor to have a predetermined threshold voltage. 
     
     
       3. The method of  claim 1 , wherein the program-inhibiting of the first selection transistors is performed by bitline biasing. 
     
     
       4. The method of  claim 3 , wherein the step of bitline biasing comprises applying to a bitline a voltage higher than zero. 
     
     
       5. The method of  claim 1 , wherein the first selection transistor is a string selection transistor SST, and the first selection line is a string selection line SSL. 
     
     
       6. The method of  claim 1 , wherein the first selection transistor is a ground selection transistor GST, and the first selection line is a ground selection line GSL. 
     
     
       7. The method of  claim 1 , wherein the memory cell transistors of the flash memory device are memory transistors of the charge trap type. 
     
     
       8. The method of  claim 1 , wherein the memory cell transistors of the flash memory device are memory transistors of the floating gate type and wherein the first selection transistors are memory transistors of the floating gate type. 
     
     
       9. A method of operating a nonvolatile memory device including a plurality of memory blocks including a first memory block, the first memory block including a plurality of cell strings including a first cell string and a second cell string, each of the first cell string and the second cell string including a plurality of nonvolatile memory cell transistors that are connected in series, the first cell string including a first string selection transistor, the second cell string including a second string selection transistor, the first string selection transistor and the second string selection transistor being connected to a string selection line, the method comprising:
 programming the first string selection transistor by applying a program voltage to the string selection line and a program bitline voltage to a first bitline connected to the first cell string; and   program-inhibiting the second string selection transistor by applying an inhibit voltage higher than the program bitline voltage to a second bitline connected to the second cell string while the applying the program voltage to the string selection line;   wherein the first string selection transistor is disposed between the first bitline and the plurality of nonvolatile memory cell transistors of the first cell string,   the second string selection transistor is disposed between the second bitline and the plurality of nonvolatile memory cell transistors of the second cell string, and   each of the first selection transistor and the second selection transistor is the same type of transistor as a type of the plurality of nonvolatile memory cell transistors,   wherein the first cell string includes a first ground selection transistor that is connected to a ground selection line and disposed between a source line and the plurality of nonvolatile memory cell transistors of the first cell string,   the second cell string includes a second ground selection transistor that is connected to the ground selection line and disposed between the source line and the plurality of nonvolatile memory cell transistors of the second cell string, and   each of the first ground selection transistor and the second ground selection transistor is a different type of transistor from a type of the plurality of nonvolatile memory cell transistors.   
     
     
       10. The method of claim 9, further comprising applying a plurality of wordline voltages to a plurality of wordlines connected to the plurality of nonvolatile memory cell transistors of each of the first cell string and the second cell string during the applying of the program voltage to the string selection line,
 wherein the program voltage is higher than each of the plurality of wordline voltages.   
     
     
       11. The method of claim 10, wherein the program bitline voltage is a ground voltage. 
     
     
       12. The method of claim 11, wherein the inhibit voltage is generated from a power supply voltage. 
     
     
       13. The method of claim 9, further comprising erasing the plurality of nonvolatile memory cell transistors in the first memory block before the programming of the first string selection transistor. 
     
     
       14. The method of claim 9, further comprising performing a verification operation to verify a program status of the first string selection transistor by applying a verify voltage to the string selection line. 
     
     
       15. The method of claim 14, further comprising applying a plurality of read voltages to the plurality of wordlines during the applying of the verify voltage to the string selection line,
 wherein the verify voltage is lower than each of the plurality of read voltages.   
     
     
       16. The method of claim 9, further comprising receiving data from an external device,
 wherein the programming of the first string selection transistor and the program-inhibiting of the second string selection transistor are performed based on the data.   
     
     
       17. The method of claim 9, further comprising applying a plurality of wordline voltages to a plurality of wordlines connected to the plurality of nonvolatile memory cell transistors of each of the first cell string and the second cell string during the applying of the program voltage to the string selection line,
 wherein the program voltage is higher than each of the plurality of wordline voltages, and   the plurality of nonvolatile memory cell transistors of each of the first cell string and the second cell string are exclusively disposed and adjacent to one another.   
     
     
       18. The method of claim 9, wherein the plurality of nonvolatile memory cell transistors are a charge trap type. 
     
     
       19. A method of operating a nonvolatile memory device including a plurality of memory blocks including a first memory block, the first memory block including a plurality of cell strings including a first cell string and a second cell string, each of the first cell string and the second cell string including a plurality of nonvolatile memory cell transistors that are connected in series, the first cell string including a first string selection transistor, the second cell string including a second string selection transistor, the first string selection transistor and the second string selection transistor being connected to a string selection line, the method comprising:
 performing a first program loop comprising:
 applying a first program voltage to the string selection line to program the first string selection transistor; 
 during the applying of the first program voltage to the string selection line, applying a plurality of wordline voltages to a plurality of wordlines connected to the plurality of nonvolatile memory cell transistors, the first program voltage being higher than each of the plurality of wordline voltages; 
 during the applying of the first program voltage to the string selection line, applying a program bitline voltage to a first bitline connected to the first cell string; 
 during the applying of the first program voltage to the string selection line, applying an inhibit voltage higher than the program bitline voltage to a second bitline connected to the second cell string; 
 applying a verify voltage to the string selection line to verify a program status of the first string selection transistor; and 
 obtaining a verify result corresponding to the program status of the first string selection transistor; and 
   performing a second program loop following the first program loop, the second program loop comprising:
 applying a second program voltage to the string selection line to increase a threshold voltage of the first string selection transistor; and 
 applying the verify voltage to the string selection line to verify the program status of the first string selection transistor after applying the second program voltage, 
   wherein the first string selection transistor is disposed between the first bitline and the plurality of nonvolatile memory cell transistors of the first cell string,   the second string selection transistor is disposed between the second bitline and the plurality of nonvolatile memory cell transistors of the second cell string, and   each of the first selection transistor and the second selection transistor is the same type of transistor as a type of the plurality of nonvolatile memory cell transistors,   wherein the first cell string includes a first ground selection transistor that is connected to a ground selection line and disposed between a source line and the plurality of nonvolatile memory cell transistors of the first cell string,   the second cell string includes a second ground selection transistor that is connected to the ground selection line and disposed between the source line and the plurality of nonvolatile memory cell transistors of the second cell string, and   each of the first ground selection transistor and the second ground selection transistor is a different type of transistor from a type of the plurality of nonvolatile memory cell transistors.   
     
     
       20. The method of claim 19, wherein the program bitline voltage is a ground voltage. 
     
     
       21. The method of claim 20, wherein the inhibit voltage is generated from a power supply voltage. 
     
     
       22. The method of claim 19, further comprising erasing the plurality of nonvolatile memory cell transistors in the first memory block before the performing of the first program loop. 
     
     
       23. The method of claim 19, further comprising receiving data from an external device,
 wherein the programming of the first string selection transistor and the program-inhibiting of the second string selection transistor are performed based on the data.   
     
     
       24. The method of claim 19, wherein the program voltage is higher than each of the plurality of wordline voltages, and
 the plurality of nonvolatile memory cell transistors of each of the first cell string and the second cell string are exclusively disposed and adjacent to one another.   
     
     
       25. The method of claim 19, wherein the plurality of nonvolatile memory cell transistors are a charge trap type. 
     
     
       26. A method of operating a nonvolatile memory device including a plurality of memory blocks including a first memory block, the first memory block including a plurality of cell strings including a first cell string and a second cell string, each of the first cell string and the second cell string including a plurality of nonvolatile memory cell transistors that are connected in series, the first cell string including a first string selection transistor, the second cell string including a second string selection transistor, the first string selection transistor and the second string selection transistor being connected to a string selection line, the method comprising:
 programming the first string selection transistor by applying a program voltage to the string selection line and a program bitline voltage to a first bitline connected to the first cell string; and   program-inhibiting the second string selection transistor by floating a second bitline connected to the second cell string during the applying of the program voltage to the string selection line;   wherein the first string selection transistor is disposed between the first bitline and the plurality of nonvolatile memory cell transistors of the first cell string,   the second string selection transistor is disposed between the second bitline and the plurality of nonvolatile memory cell transistors of the second cell string, and   each of the first selection transistor and the second selection transistor is the same transistor type as the plurality of nonvolatile memory cell transistors,   wherein the first cell string includes a first ground selection transistor that is connected to a ground selection line and disposed between a source line and the plurality of nonvolatile memory cell transistors of the first cell string,   the second cell string includes a second ground selection transistor that is connected to the ground selection line and disposed between the source line and the plurality of nonvolatile memory cell transistors of the second cell string, and   each of the first ground selection transistor and the second ground selection transistor is a different transistor type from the plurality of nonvolatile memory cell transistors.   
     
     
       27. The method of claim 26, wherein the plurality of nonvolatile memory cell transistors are memory transistors of the charge trap type, and
 the first selection transistor and the second selection transistor are memory transistors of the charge trap type.