Power semiconductor device

Abstract

A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.

What is claimed is: 
     
       1. A power semiconductor device comprising:
 a first base layer of a first conductivity type; 
 a collector layer of a second conductivity type disposed on the first base layer; 
 a plurality of trenches disposed in the first base layer at intervals to partition a main cell and a dummy cell, at a position remote from the collector layer; 
 a second base layer of the second conductivity type disposed on the first base layer in the main cell; 
 an emitter layer of the first conductivity type disposed on the second base layer; 
 a buffer layer of the second conductivity type disposed on the first base layer in the dummy cell; 
 a gate electrode disposed in a trench of the plurality of trenches, adjacent to the main cell, to face, through a gate insulating film, a portion of the second base layer sandwiched between the first base layer and the emitter layer; 
 a collector electrode disposed on the collector layer; 
 an emitter electrode disposed on the second base layer and the emitter layer; and 
 a buffer resistor inserted between the buffer layer and the emitter electrode and having an infinitely large resistance value, 
 wherein the main cell forms a current passage narrow enough to provide, in an on-state of the device, an increase in resistance against flow of carriers of the second conductivity type from the first base layer into the emitter electrode through the second base layer, thereby improving injection efficiency of carriers of the first conductivity type from the emitter layer into the first base layer, and 
 the dummy cell is provided with an inhibiting structure configured to reduce a quantity of carriers of the second conductivity type to that flow to and accumulate in the buffer layer from the collector layer, in a period of time for during which an applied voltage between a gate and an emitter to charge capacity a capacitance between the gate electrode and the emitter, in electrode is applied during a process of turn-on of the power semiconductor device, the quantity of carriers of the second conductivity type being reduced as compared to a case where in which the buffer layer and the second base layer are formed with the same impurity concentration and depth as each other. 
 
     
     
       2. The device according to  claim 1 , wherein the inhibiting structure comprises a structure in which the buffer layer has a depth for setting an pn junction between the first base layer and the buffer layer to be positioned that is deeper than a bottom of the plurality of trenches. 
     
     
       3. The device according to  claim 2 , wherein the buffer layer has an impurity concentration of 1×10 14  cm −3  or more at a position adjacent to a the bottom of the plurality of trenches, and a difference in depth between the bottom of the plurality of trenches and a deepest portion of the a pn junction between the first base layer and the buffer layer is 0.5 μm or more. 
     
     
       4. The device according to  claim 1 , wherein the inhibiting structure comprises a structure in which a second distance between a pair of trenches sandwiching a first trench and a second trench in the plurality of trenches sandwiches the dummy cell adjacent to and the main cell is sandwiched between the second trench and a third trench in the plurality of trenches, the first and second trenches being spaced from each other by a second distance that is smaller than a first distance between a pair of trenches sandwiching the main cell by which the second and third trenches are spaced from each other. 
     
     
       5. The device according to  claim 4 , wherein a ratio of the second distance to the first distance is ⅔ or less. 
     
     
       6. The device according to  claim 1 , wherein the inhibiting structure comprises a structure in which a second depth of a dummy trench of the plurality of trenches that is adjacent not to the main cell but to the dummy cell but not adjacent to the main cell is larger than a first depth of a trench in the plurality of trenches that is adjacent to the main cell. 
     
     
       7. The device according to claim  1  6, wherein a difference between the second depth and the first depth is 1 μm or more. 
     
     
       8. The device according to  claim 1 , wherein the inhibiting structure comprises a structure in which a projecting layer of the second conductivity type is formed in the first base layer and in contact with a bottom of a dummy trench in the plurality of trenches that is adjacent not to the main cell but to the dummy cell but not adjacent to the main cell. 
     
     
       9. The device according to  claim 8 , wherein the projecting layer reaches a depth of 1 μm or more from the bottom of the dummy trench. 
     
     
       10. The device according to  claim 1 , wherein a trench in the plurality of trenches that is adjacent not to the main cell but to the dummy cell but not adjacent to the main cell is provided with a dummy electrode wrapped in an insulating film, and the dummy electrode is electrically connected to the emitter electrode. 
     
     
       11. The device according to  claim 1 , wherein the buffer layer is in an electrically floating state. 
     
     
       12. The device according to  claim 1 , wherein the trenches in the plurality of trenches are disposed to partition the main cell and two dummy cells between which, and the main cell is interposed between the two dummy cells, and each of the two dummy cells is provided with the buffer layer, the buffer resistor and has the inhibiting structure. 
     
     
       13. The device according to  claim 3 , wherein the difference in the depth between the bottom of the plurality of trenches and a the deepest portion of the pn junction between the first base layer and the buffer layer is 1 μm or more. 
     
     
       14. The device according to  claim 1 , wherein the buffer layer is electrically isolated from the second base layer and the emitter electrode by the plurality of trenches and an insulating film disposed on the buffer layer. 
     
     
       15. The device according to  claim 14 , wherein, in a channel width direction of a channel induced by the gate electrode in the portion of the second base layer sandwiched between the first base layer and the emitter layer, the plurality of trenches have a length larger than extend beyond ends of the second base layer and the buffer layer to separate the second base layer and the buffer layer, the channel width direction being perpendicular to a depth direction of the plurality of trenches towards the collector layer. 
     
     
       16. The device according to  claim 15 , wherein a layer of the first conductivity type is disposed over the ends of the second base layer and the buffer layer in the channel width direction. 
     
     
       17. The device according to  claim 3 , wherein the buffer layer is in an electrically floating state. 
     
     
       18. The device according to  claim 17 , wherein the buffer layer is electrically isolated from the second base layer and the emitter electrode by the plurality of trenches and an insulating film disposed on the buffer layer resistor. 
     
     
       19. The device according to  claim 18 , wherein, in a channel width direction of a channel induced by the gate electrode in the portion of the second base layer sandwiched between the first base layer and the emitter layer, the plurality of trenches have a length larger than extend beyond ends of the second base layer and the buffer layer to separate the second base layer and the buffer layer, the channel width direction being perpendicular to a depth direction of the plurality trenches towards the collector layer. 
     
     
       20. The device according to  claim 19 , a layer of the first conductivity type is disposed over the ends of the second base layer and the buffer layer in the channel width direction. 
     
     
       21. A power semiconductor device comprising:
 a first base layer of a first conductivity type;   a collector layer of a second conductivity type disposed on the first base layer;   a plurality of trenches disposed in the first base layer at intervals to partition a main cell and dummy cells, at a position remote from the collector layer;   a second base layer of the second conductivity type disposed on the first base layer in the main cell;   an emitter layer of the first conductivity type disposed on the second base layer;   a buffer layer of the second conductivity type disposed on the first base layer in the dummy cells;   a gate electrode disposed in a first trench of the plurality of trenches, the first trench being adjacent to the main cell, to face, through a gate insulating film, a portion of the second base layer sandwiched between the first base layer and the emitter layer;   a collector electrode disposed on the collector layer;   an emitter electrode disposed on the second base layer and the emitter layer; and   a buffer resistor inserted between the buffer layer and the emitter electrode and having an infinitely large resistance value, the buffer resistor comprising an insulating film,   wherein the main cell is provided between a pair of dummy cells,   wherein the main cell forms a current passage narrow enough to provide, in an on-state of the device, an increase in resistance against flow of carriers of the second conductivity type from the first base layer into the emitter electrode through the second base layer, thereby improving injection efficiency of carriers of the first conductivity type from the emitter layer into the first base layer, and   the dummy cells are each provided with an inhibiting structure in which the buffer layer extends along a depth direction from the emitter electrode towards the collector electrode to be closer to the collector electrode than is the second base layer to the collector electrode, the inhibiting structure configured to reduce a quantity of carriers of the second conductivity type that flow to and accumulate in the buffer layer from the collector layer, in a period of time during which an applied voltage between a gate and an emitter to charge a capacitance between the gate electrode and the emitter electrode is applied during a process of turn-on of the power semiconductor device, the quantity of carriers of the second conductivity type being reduced as compared to a case in which the buffer layer and the second base layer are formed with the same impurity concentration and depth as each other.   
     
     
       22. The device according to claim 21, wherein the buffer layer and the first base layer together form a pn junction at a depth that is location deeper than a bottom of the plurality of trenches in the depth direction. 
     
     
       23. The device according to claim 22, wherein the buffer layer has an impurity concentration of 1×10 14  cm −3  or more at a position adjacent to the bottom of the plurality of trenches, and a difference in depth in the depth direction between the bottom of the plurality of trenches and a deepest portion of the pn junction in the depth direction is 0.5 μm or more. 
     
     
       24. The device according to claim 21, wherein a distance between adjacent trenches in the plurality trenches across one of the dummy cells is smaller than a distance between adjacent trenches in the plurality of trenches across the main cell. 
     
     
       25. The device according to claim 24, wherein the ratio of the distance between adjacent trenches in the plurality trenches across one of the dummy cells a and the distance between adjacent trenches in the plurality of trenches across the main cell is ⅔ or less. 
     
     
       26. The device according to claim 21, wherein a depth of a second trench in the plurality trenches that is directly adjacent to one of the adjacent dummy cells but spaced from the main cell is greater than a depth of the first trench in the plurality of trenches. 
     
     
       27. The device according to claim 26, wherein the difference between the depths of the second trench and the first trench is 1 μm or more. 
     
     
       28. The device according to claim 21, further comprising a layer of the second conductivity type within the first base layer and in contact with a bottom of a dummy trench in the plurality of trenches that is spaced from the main cell. 
     
     
       29. The device according to claim 28, wherein the layer of the second conductivity type extends in the depth direction 1 μm or more from the bottom of the dummy trench. 
     
     
       30. The device according to claim 21, wherein a second trench in the plurality of trenches that is spaced from the main cell and directly adjacent to one of the dummy cells includes a dummy electrode wrapped in an insulating film, and the dummy electrode is electrically connected to the emitter electrode. 
     
     
       31. The device according to claim 21, wherein the buffer layer is electrically floating. 
     
     
       32. The device according to claim 21, wherein trenches in the plurality of trenches are disposed to partition the main cell, a first pair of adjacent dummy cells, and a second pair of adjacent dummy cells, the main cell being between the first pair and the second pair of dummy cells. 
     
     
       33. The device according to claim 23, wherein the difference in depth between the bottom of the plurality of trenches and the deepest portion of the pn junction is 1 μm or more. 
     
     
       34. The device according to claim 21, wherein the buffer layer is electrically isolated from the second base layer and the emitter electrode by the plurality of trenches and an insulating film disposed on the buffer layer. 
     
     
       35. The device according to claim 34, wherein the plurality of trenches extend beyond ends of the second base layer and the buffer layer in a channel width direction that is perpendicular to the depth direction of the plurality of trenches. 
     
     
       36. The device according to claim 35, wherein a layer of the first conductivity type is disposed over the ends of the second base layer and the buffer layer. 
     
     
       37. The device according to claim 23, wherein the buffer layer is in an electrically floating state. 
     
     
       38. The device according to claim 37, wherein the buffer layer is electrically isolated from the second base layer and the emitter electrode by the plurality of trenches and an insulating film disposed on the buffer layer. 
     
     
       39. The device according to claim 38, wherein, in a channel width direction of a channel, the plurality of trenches extend beyond ends of the second base layer and the buffer layer, the channel width direction being perpendicular to the depth direction of the plurality of trenches.