Non-volatile semiconductor storage device

Abstract

A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.

What is claimed is: 
     
       1. A non-volatile semiconductor storage device comprising:
 a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and   a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells;   each of the plurality of transfer transistors comprising:   a gate electrode formed on a semiconductor substrate via a gate insulation film;   diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers; and   upper layer wirings provided above the diffusion layers,   wherein   the transfer transistors comprise enhancement-type transistors and depression-type transistors,   the upper layer wirings provided above the transfer transistors corresponding to the enhancement-type transistors are provided with a predetermined voltage at least when the transfer transistors become conductive to prevent depletion of the diffusion layer, and   the upper layer wirings provided above the transfer transistors corresponding to the depression-type transistors are supplied with a fixed voltage smaller than a voltage applied to their gates.   
     
     
       2. The non-volatile semiconductor storage device according to  claim 1 , further comprising:
 a row decoder selecting a word line provided above the memory cell array,   wherein the transfer transistors are included in the row decoder.   
     
     
       3. The non-volatile semiconductor storage device according to  claim 1 , wherein
 the upper layer wirings of the transfer transistors corresponding to the enhancement-type transistors are provided with the same voltage as that of the gate electrode.   
     
     
       4. The non-volatile semiconductor storage device according to  claim 3 , wherein
 the upper layer wirings of the transfer transistors corresponding to the enhancement-type transistors are short-circuited to the gate electrode.   
     
     
       5. The non-volatile semiconductor storage device according to  claim 1 , wherein
 the upper layer wirings of the transfer transistors corresponding to the enhancement-type transistors are provided with the same voltage as that of the diffusion layers.   
     
     
       6. The non-volatile semiconductor storage device according to  claim 5 , wherein
 the upper layer wirings of the transfer transistors corresponding to the enhancement-type transistors are short-circuited to the diffusion layers.   
     
     
       7. The non-volatile semiconductor storage device according to  claim 1 , further comprising:
 a short-circuit wiring short-circuiting the upper layer wirings to the gate electrode.   
     
     
       8. The non-volatile semiconductor storage device according to  claim 1 , wherein
 the memory cell array comprises NAND cells including a plurality of serially-connected memory cells, and selection transistors connected to the NAND cells.   
     
     
       9. The non-volatile semiconductor storage device according to  claim 1 , wherein
 each of the diffusion layers comprises a high concentration area with a first impurity concentration and an LDD area with a second impurity concentration lower than the first impurity concentration.   
     
     
       10. The non-volatile semiconductor storage device according to  claim 9 , wherein
 the upper layer wirings are provided above the LDD areas.   
     
     
       11. The non-volatile semiconductor storage device according to  claim 1 , wherein
 the plurality of transfer transistors share the gate electrode as well as the upper layer wirings that are disposed in a continuous manner.   
     
     
       12. The non-volatile semiconductor storage device according to  claim 1 , wherein
 the plurality of transfer transistors share the gate electrode, and   the upper layer wirings are separately disposed for one or two of the plurality of transfer transistors.   
     
     
       13. The non-volatile semiconductor storage device according to  claim 1 , further comprising:
 a signal line electrically connected to the diffusion layers,   wherein the upper layer wirings are short-circuited to the signal line.   
     
     
       14. A non-volatile semiconductor storage device comprising:
 a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and   a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells;   each of the plurality of transfer transistors comprising:   a gate electrode formed on a semiconductor substrate via a gate insulation film;   diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers; and   upper layer wirings provided above the diffusion layers,   wherein   the transfer transistors comprise enhancement-type transistors and depression-type transistors,   the upper layer wirings provided above the transfer transistors corresponding to the enhancement-type transistors are provided with the same voltage as applied to the diffusion layers or the gate voltage at least when the transfer transistors become conductive, and   the upper layer wirings provided above the transfer transistors corresponding to the depression-type transistors are supplied with a fixed voltage smaller than a voltage applied to their gates.   
     
     
       15. The non-volatile semiconductor storage device according to  claim 14 , further comprising:
 a row decoder selecting a word line provided above the memory cell array,   wherein the transfer transistors are included in the row decoder.   
     
     
       16. The non-volatile semiconductor storage device according to  claim 14 , wherein
 the upper layer wirings of the transfer transistors corresponding to the enhancement-type transistors are short-circuited to the gate electrode.   
     
     
       17. The non-volatile semiconductor storage device according to  claim 14 , wherein
 the upper layer wirings of the transfer transistors corresponding to the enhancement-type transistors are short-circuited to the diffusion layers.   
     
     
       18. A non-volatile semiconductor storage device comprising:
 a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and   a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells;   each of the plurality of transfer transistors comprising:   a gate electrode formed on a semiconductor substrate via a gate insulation film;   diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers; and   upper layer wirings provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive,   wherein the plurality of transfer transistors share the gate electrode, and   the upper layer wirings are separately disposed for one or two of the plurality of transfer transistors.   
     
     
       19. A non-volatile semiconductor storage device comprising:
 a memory cell array including a plurality of memory cells;   a plurality of transfer transistors configured to transfer a voltage to the memory cells, the transfer transistors including a first transfer transistor and a second transfer transistor, the first transfer transistor comprising first drain/source regions, the second transfer transistor comprising second drain/source regions, the first and second transfer transistors comprising a common gate electrode extending in a first direction; and   wirings provided above the first drain/source regions and the second drain/source regions, the wirings including a first wiring, the first wiring comprising a first portion, a second portion, and a third portion each provided above one of the first drain/source regions, the first portion and the third portion extending in the first direction, the second portion extending in a second direction crossing the first direction, the first portion being connected to the one of the first drain/source regions via a first contact, and the second portion and the third portion being provided between the first portion and the common gate electrode, the second portion being connected to the first portion and the third portion.    
     
     
       20. The non-volatile semiconductor storage device according to claim 19, wherein
 the first wiring connects to gates of the memory cells.    
     
     
       21. The non-volatile semiconductor storage device according to claim 19, further comprising a row decoder selecting a word line provided above the memory cell array, wherein
 the first and second transfer transistors are included in the row decoder.    
     
     
       22. The non-volatile semiconductor storage device according to claim 19, wherein
 the first wiring further comprises a fourth portion extending in the first direction and connected to the second portion.    
     
     
       23. The non-volatile semiconductor storage device according to claim 19, wherein
 both the first portion and the second portion are arranged in a same layer.    
     
     
       24. The non-volatile semiconductor storage device according to claim 19, wherein
 the wirings includes a second wiring, a third wiring and a fourth wiring,   the second wiring comprises a fourth portion extending in the first direction and connected to another one of the first drain/source regions via a second contact, and   the third wiring and the fourth wiring are provided between the fourth portion and the common gate electrode.    
     
     
       25. The non-volatile semiconductor storage device according to claim 24, wherein
 the second wiring connects to gates of the memory cells.    
     
     
       26. The non-volatile semiconductor storage device according to claim 24, wherein
 both the first wiring and the second wiring are arranged in a same layer.    
     
     
       27. The non-volatile semiconductor storage device according to claim 19, wherein
 the wirings includes a fifth wiring comprising a fifth portion, a sixth portion, and a seventh portion each provided above one of the second drain/source regions, the fifth portion and seventh portion extending in the first direction, the sixth portion extending in the second direction, the fifth portion being connected to the one of the second drain/source regions via a third contact, and the sixth portion and the seventh portion being provided between the fifth portion and the common gate electrode, the sixth portion being connected to the fifth portion and the seventh portion.    
     
     
       28. The non-volatile semiconductor storage device according to claim 24, wherein the wirings includes a sixth wiring,
 the sixth wiring includes an eighth portion extending in the first direction and connected to another one of the second drain/source regions via a fourth contact, and   the second wiring and the third wiring are provided between a sixth portion and the common gate electrode.