Layout for multiple-fin SRAM cell

Abstract

The present disclosure provides a static random access memory (SRAM) cell. The SRAM cell includes a plurality of fin active regions formed on a semiconductor substrate, wherein the plurality of fin active regions include a pair adjacent fin active regions having a first spacing and a fin active region having a second spacing from adjacent fin active regions, the second spacing being greater than the first spacing; a plurality of fin field-effect transistors (FinFETs) formed on the plurality of fin active regions, wherein the plurality of FinFETs are configured to a first and second inverters cross-coupled for data storage and at least one port for data access; a first contact disposed between the first and second the fin active regions, electrically contacting both of the first and second the fin active regions; and a second contact disposed on and electrically contacting the third fin active region.

What is claimed is: 
     
       1. A device comprising:
 a first fin active region, a second fin active region, and a third fin active region extending from a semiconductor substrate, wherein the first and second fin active regions are spaced apart from each other first fin is spaced away from the second fin by a first distance and the second and third fin active regions are spaced apart from each other the second fin is spaced away from the third fin by a second distance, wherein the second distance is different greater than the first distance, wherein the first fin includes a first source region and a first drain region, the second fin includes a second source region and a second drain region, and the third fin includes a third source region and a third drain region; 
 a plurality of fin field-effect transistors (FinFETs) formed on at least one of the first, second, and third fin active regions; 
 a gate structure wrapping the first fin, the second fin, and the third fin, such that the gate structure traverses the first source region and the first drain region of the first fin, the second source region and the second drain region of the second fin, and the third source region and the third drain region of the third fin; 
 first epitaxy features disposed on the first source region and the first drain region of the first fin, second epitaxy features disposed on the second source region and the second drain region of the second fin, and third epitaxy features disposed on the third source region and the third drain region of the third fin, wherein the second epitaxy feature disposed on the second source region is merged with the first epitaxy feature disposed on the first source region, and further wherein the second epitaxy feature disposed on the second source region is not merged with the third epitaxy feature disposed on the third source region;  
 a first contact disposed on the first and second fin active regions a portion of the first epitaxy feature and a portion of the second epitaxy feature disposed respectively on the first source region of the first fin and the second source region of the second fin, such that the first contact couples the first source region of the first fin and the second source region of the second fin to a first voltage line; and 
 a second contact disposed on a portion of the third epitaxy feature disposed on the third source region of the third fin, such that the second contact couples the third source region of the third fin active region to a second voltage line; and 
 a first isolation feature disposed between the first fin and the second fin and a second isolation feature disposed between the second fin and the third fin, wherein:
 the first, second, and third fins are recessed, such that top surfaces of the first, second, and third fins are lower than top surfaces of the first and second isolation features, and 
 the first, second, and third epitaxy features are disposed respectively over the top surfaces of the first, second, and third fins, such that a portion of the second epitaxy features is disposed between the first isolation feature and the second isolation feature. 
 
 
     
     
       2. The device of  claim 1 , further comprising a fourth fin active region extending from the semiconductor substrate, wherein the third and fourth fin active regions are spaced way from each other is spaced away from the third fin by the second distance. 
     
     
       3. The device of  claim 1 , wherein the second distance is greater than the first distance. 
     
     
       4. The device of  claim 1 , wherein at least one of the first and second fin active regions includes an epitaxy feature formed thereon the second epitaxy feature disposed on the second drain region is merged with the first epitaxy feature disposed on the first drain region and is not merged with the third epitaxy feature disposed on the third drain region, the device further comprising:
 a third contact disposed on a portion of the first epitaxy feature and a portion of the second epitaxy feature disposed respectively on the first drain region and the second drain region, such that the third contact couples the first drain region of the first fin and the second drain region of the second fin. 
 
     
     
       5. The device of claim  4  1, wherein the first epitaxy feature includes at least one of silicon germanium and silicon carbide features and the second epitaxy features include a first material, and the third epitaxy features include a second material that is different than the first material. 
     
     
       6. The device of  claim 1 , wherein the first contact physically contacts the first and second fin active regions. 
     
     
       7. The device of  claim 1 , wherein the plurality of FinFETs include:
 a first inverter including a first pull-up transistor (PU- 1 ) and a first and second pull-down transistors (PD- 1  and PD- 2 ); and   a second inverter including a second pull-up transistor (PU- 2 ) and a third and fourth pull-down transistors (PD- 3  and PD- 4 ), the second inverter being cross-coupled with the first inverter for data storage, and   wherein the PD- 1  and PD- 2  are formed on the first and second fin active regions, respectively.   
     
     
       8. A device comprising:
 a first fin active region, a second fin active region, and a third fin active region extending from a semiconductor substrate;   a first isolation element extending a first distance from the first fin active region to the second fin active region;   a second isolation element extending a second distance from the second fin active region to the third fin active region, wherein the second distance is different than the first distance;   a plurality of fin field-effect transistors (FinFETs) formed on at least one of the first, second, and third fin active regions;   a first contact disposed on the first and second fin active regions; and   a second contact disposed on the third fin active region.   
     
     
       9. The device of  claim 8 , wherein the first and second fin active regions have a first silicon epitaxy feature and a second silicon epitaxy feature, respectively. 
     
     
       10. The device of  claim 9 , further comprising a silicide feature formed on the first and second silicon epitaxy features. 
     
     
       11. The device of  claim 8 , further comprising a fourth fin active region extending from the semiconductor substrate; and
 a third isolation element extending the second distance from the third fin active region to the fourth fin active region.   
     
     
       12. The device of  claim 11 , wherein the second contact is not electrically coupled to the fourth fin active region. 
     
     
       13. The device of  claim 8 , wherein the plurality of FinFETs includes:
 a first pull-up device and a second pull-up device;   a first pull-down device configured with the first pull-up device to form a first inverter;   a second pull-down device configured with the second pull-up device to form a second inverter; and   a first and second pass-gate devices configured with the first and second inverters as a first port.   
     
     
       14. The device of claim 1, wherein the first contact is disposed between the first fin and the second fin, such that the first contact is disposed on an interface between the first epitaxy feature disposed on the first source region of the first fin and the second epitaxy feature disposed on the second source region of the second fin. 
     
     
       15. The device of claim 1, wherein the first contact spans the first distance between the first fin and the second fin and extends beyond outermost sidewalls of the first fin and the second fin. 
     
     
       16. The device of claim 1, wherein the first contact spans the first distance between the first fin and the second fin and does not extend beyond outermost sidewalls of the first fin and the second fin. 
     
     
       17. The device of claim 1, wherein the first, second, and third fins are respectively a portion of a first, a second, and a third fin field-effect transistors (FinFETs). 
     
     
       18. The device of claim 1, wherein the gate structure includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. 
     
     
       19. The device of claim 18, wherein the gate dielectric layer includes at least one high-k dielectric material layer. 
     
     
       20. The device of claim 18, wherein the gate electrode includes metal. 
     
     
       21. The device of claim 20, wherein the gate electrode includes aluminum, copper, tungsten, or a combination thereof. 
     
     
       22. The device of claim 18, wherein the first, second, and third fins oriented in a first direction and the gate structure oriented in a second direction substantially perpendicular to the first direction. 
     
     
       23. The device of claim 17, wherein the first, second, and third fin field-effect transistors (FinFETs) are a portion of a SRAM cell. 
     
     
       24. The device of claim 23, wherein at least one of the first, second, and third fin field-effect transistors (FinFETs) is a pull-down transistor of the SRAM cell. 
     
     
       25. The device of claim 23, wherein at least one of the first, second, and third fin field-effect transistors (FinFETs) is a pass gate transistor of the SRAM cell. 
     
     
       26. The device of claim 23, wherein at least one of the first, second, and third fin field-effect transistors (FinFETs) is a pull-up transistor of the SRAM cell. 
     
     
       27. The device of claim 23, wherein the first and second fin field-effect transistors (FinFETs) are pull-down transistors of the SRAM cell. 
     
     
       28. The device of claim 23, wherein the first and second fin field-effect transistors (FinFETs) are pass gate transistors of the SRAM cell. 
     
     
       29. The device of claim 1, wherein the first contact is disposed directly adjacent to the second contact. 
     
     
       30. The device of claim 29, wherein the first, second, and third fins extend along a first direction, and the first and second contacts extend along a second direction that is substantially perpendicular to the first direction. 
     
     
       31. The device of claim 29, wherein a width of the first, second, and third fins is along the second direction, and further wherein the first contact extends beyond the first fin and the second fin along the second direction. 
     
     
       32. The device of claim 29, wherein the first contact does not overlap the first fin and the second fin. 
     
     
       33. The device of claim 1, wherein there is no fin between the first and the second fins along an entire length of the first and the second fins, and there is no fin between the second and the third fins along an entire length of the second and third fins. 
     
     
       34. The device of claim 1, wherein a dimension of the first contact is greater than a dimension of the second contact. 
     
     
       35. The device of claim 1, wherein a dimension of the first contact and a dimension of the second contact are substantially the same. 
     
     
       36. The device of claim 1, wherein the substrate includes silicon, germanium, silicon germanium, or a combination thereof. 
     
     
       37. The device of claim 36, wherein the substrate further includes a dielectric layer. 
     
     
       38. The device of claim 37, wherein the dielectric layer includes silicon oxide. 
     
     
       39. The device of claim 37, wherein the substrate further includes a semiconductor on insulator (SOI) layer formed on the dielectric layer. 
     
     
       40. The device of claim 1, further comprising a shallow trench isolation (STI) layer formed on the substrate, wherein the first, second, and third fins are in the STI layer. 
     
     
       41. The device of claim 40, further comprising an interlayer dielectric (ILD) layer over the STI layer, wherein the first and second contacts are in the ILD layer. 
     
     
       42. The device of claim 41, wherein the ILD layer includes silicon dioxide, silicon nitride, silicon oxynitride, polyimide, spin-on glass (SOG), fluoride-doped silicate glass (FSG), carbon doped silicon oxide, Black Diamond® (Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB (bis-benzocyclobutenes), SiLK (Dow Chemical, Midland, Mich.), or a combination thereof. 
     
     
       43. The device of claim 1, wherein at least one of the first and second contacts includes tungsten, aluminum, copper, titanium, nickel, cobalt, platinum, palladium tungsten, tantalum, erbium, or a combination thereof. 
     
     
       44. The device of claim 1, further comprising a barrier layer formed on sidewalls of at least one of the first and second contacts. 
     
     
       45. The device of claim 44, wherein the barrier layer includes titanium nitride. 
     
     
       46. The device of claim 1, further comprising a silicide feature disposed between the first contact and the first epitaxy feature and the second epitaxy feature. 
     
     
       47. The device of claim 46, wherein the silicide feature includes titanium, cobalt, nickel, molybdenum, platinum, or a combination thereof. 
     
     
       48. A device comprising:
 a first fin of a first fin field effect transistor (FinFET), a second fin of a second FinFET, a third fin of a third FinFET, a fourth fin of a fourth FinFET, wherein the first, second, third, and fourth fins are oriented substantially parallel to one another, the first fin and the second fin are separated by a first distance, the third fin and the fourth fin are separated by a second distance that is greater than the first distance, the first FinFET and the second FinFET are first type FinFETs, the third FinFETs and the fourth FinFETs are second type FinFETs, and the first type is opposite the second type;   a single gate structure that traverses the first, second, third, and fourth fins, such that the gate structure wraps a first portion respectively of the first, second, third, and fourth fins;   a first epitaxy feature disposed on a second portion of the first fin, a second epitaxy feature disposed on a second portion of the second fin, a third epitaxy feature disposed on a second portion of the third fin, and a fourth epitaxy feature disposed on a second portion of the fourth fin, wherein the first epitaxy feature is merged with the second epitaxy feature and the third epitaxy feature is not merged with the fourth epitaxy feature;   a first contact disposed on the first epitaxy feature and the second epitaxy feature, wherein the first contact spans the first distance between the first fin and the second fin;   a second contact disposed on the third epitaxy feature and the fourth epitaxy feature, wherein the second contact spans the second distance between the third fin and the fourth fin.   
     
     
       49. The device of claim 48, wherein the second fin is separated from the third fin by the second distance. 
     
     
       50. The device of claim 48, wherein the first epitaxy feature and the second epitaxy feature include silicon or silicon carbide, and the third epitaxy feature and the fourth epitaxy feature include silicon germanium. 
     
     
       51. The device of claim 48, wherein the first epitaxy feature and the second epitaxy feature include silicon germanium, and the third epitaxy feature and the fourth epitaxy feature include silicon or silicon carbide. 
     
     
       52. The device of claim 48, wherein the first type FinFETs are n-type FinFETs and the second type FinFETs are p-type FinFETs. 
     
     
       53. The device of claim 52, further comprising a substrate that includes an n-well region and a p-well region, wherein the n-type FinFETs are disposed over the p-well region and the p-type finFETs are disposed over the n-well region. 
     
     
       54. The device of claim 48, wherein the first type FinFETs are p-type FinFETs and the second type FinFETs are n-type FinFETs. 
     
     
       55. The device of claim 54, further comprising a substrate that includes an n-well region and a p-well region, wherein the p-type FinFETs are disposed over the n-well region and the n-type finFETs are disposed over the p-well region. 
     
     
       56. The device of claim 48, wherein the second portions of the first, second, third, and fourth fins are source regions respectively of the first, second, third, and fourth FinFETs. 
     
     
       57. The device of claim 48, wherein the second portions of the first, second, third, and fourth fins are drain regions respectively of the first, second, third, and fourth FinFETs. 
     
     
       58. The device of claim 48, wherein the gate structure includes a high-k gate dielectric and a metal gate electrode. 
     
     
       59. The device of claim 48, wherein the gate structure includes a gate dielectric and a gate electrode disposed on the gate dielectric. 
     
     
       60. The device of claim 59, wherein the gate dielectric includes at least one high-k dielectric layer. 
     
     
       61. The device of claim 59, wherein at least one of the first, second, third, and fourth epitaxy features includes a top surface higher than the gate dielectric. 
     
     
       62. The device of claim 59, wherein the gate electrode includes metal. 
     
     
       63. The device of claim 62, wherein the gate electrode includes aluminum, copper, tungsten, or a combination thereof. 
     
     
       64. The device of claim 48, wherein the first, second, third, and fourth fins are oriented in a first direction and the gate structure is oriented in a second direction substantially perpendicular to the first direction. 
     
     
       65. The device of claim 48, wherein the gate structure is not formed over a source region of the first, second, third, and fourth fins. 
     
     
       66. The device of claim 48, wherein the gate structure is not formed over a drain region of the first, second, third, and fourth fins. 
     
     
       67. The device of claim 48, wherein the first, second, third, and fourth FinFETs are a portion of a SRAM cell. 
     
     
       68. The device of claim 67, wherein the first and second FinFETs are pull-down transistors of the SRAM cell, and the third and fourth FinFETs are pull-up transistors of the SRAM cell. 
     
     
       69. The device of claim 67, wherein at least one of the first, second, third, and fourth FinFETs is a pass gate transistor of the SRAM cell. 
     
     
       70. The device of claim 67, wherein the first and second FinFETs are pull-up transistors of the SRAM cell, and the third and fourth FinFETs are pull-down transistors of the SRAM cell. 
     
     
       71. The device of claim 67, wherein both the first and second fin field-effect transistors (FinFETs) are pull-down transistors of the SRAM cell. 
     
     
       72. The device of claim 67, wherein both the first and second fin field-effect transistors (FinFETs) are pass gate transistors of the SRAM cell. 
     
     
       73. The device of claim 67, wherein both the first and second fin field-effect transistors (FinFETs) are pull-up transistors of the SRAM cell. 
     
     
       74. The device of claim 48, wherein the first contact is coupled to a first metal line and the second contact is coupled to a second metal line. 
     
     
       75. The device of claim 74, wherein the first metal line is a first power line and the second metal line is a second power line. 
     
     
       76. The device of claim 75, wherein the first power line and the second power line are complementary power lines. 
     
     
       77. The device of claim 48, wherein a distance between the third epitaxy feature and the fourth epitaxy feature is less than the second distance. 
     
     
       78. The device of claim 48, wherein the second epitaxy feature is spaced away from the third epitaxy feature, wherein a distance between the second and the third epitaxy features is less than a distance between the second and the third fins. 
     
     
       79. The device of claim 48, wherein at least one of the first, second, third, and fourth epitaxy features includes a top portion having multiple surfaces for coupling with the first contact or the second contact. 
     
     
       80. The device of claim 48, wherein at least one of the first, second, third, and fourth epitaxy features includes a diamond shaped top portion. 
     
     
       81. The device of claim 48, wherein a dimension of the second contact is greater than a dimension of the first contact. 
     
     
       82. The device of claim 48, wherein there is no fin between the first and the second fins along an entire length of the first and the second fins. 
     
     
       83. The device of claim 48, wherein a dimension of the first contact is greater than a dimension of the second contact. 
     
     
       84. The device of claim 48, wherein a dimension of the first contact and a dimension of the second contact are substantially the same. 
     
     
       85. The device of claim 48, further comprising a substrate that includes silicon, germanium, silicon germanium, or a combination thereof, wherein the first, second, third, and fourth fins are disposed over the substrate. 
     
     
       86. The device of claim 85, wherein the substrate further includes a dielectric layer. 
     
     
       87. The device of claim 86, wherein the dielectric layer includes silicon oxide. 
     
     
       88. The device of claim 86, wherein the substrate further includes a semiconductor on insulator (SOI) layer formed on the dielectric layer. 
     
     
       89. The device of claim 48, further comprising shallow trench isolation (STI) layer disposed between the first, second, third, and fourth fins. 
     
     
       90. The device of claim 89, further comprising an interlayer dielectric (ILD) layer over the STI layer, wherein the first and second contacts are in the ILD layer. 
     
     
       91. The device of claim 90, wherein the ILD layer includes silicon dioxide, silicon nitride, silicon oxynitride, polyimide, spin-on glass (SOG), fluoride-doped silicate glass (FSG), carbon doped silicon oxide, Black Diamond® (Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB (bis-benzocyclobutenes), SiLK (Dow Chemical, Midland, Mich.), or a combination thereof. 
     
     
       92. The device of claim 48, wherein at least one of the first and second contacts includes tungsten, aluminum, copper, titanium, nickel, cobalt, platinum, palladium tungsten, tantalum, erbium, or a combination thereof. 
     
     
       93. The device of claim 48, further comprising a barrier layer formed on sidewalls of at least one of the first and second contacts. 
     
     
       94. The device of claim 93, wherein the barrier layer includes titanium nitride. 
     
     
       95. The device of claim 48, further comprising a silicide feature disposed between the first contact and the first and second epitaxy features and the second contact and the third and fourth epitaxy features. 
     
     
       96. The device of claim 95, wherein the silicide feature includes titanium, cobalt, nickel, molybdenum, platinum, or a combination thereof. 
     
     
       97. The device of claim 48, wherein the second fin and the third fin are separated by a third distance that is the same as the second distance. 
     
     
       98. The device of claim 48, wherein the second fin and the third fin are separated by a third distance that is greater than the first distance. 
     
     
       99. The device of claim 48, wherein there is no fin between the third and the fourth fins along an entire length of the third and the fourth fins. 
     
     
       100. The device of claim 48, further comprising:
 a fifth fin of a fifth FinFET, wherein the fifth fin is oriented substantially parallel to the first, second, third, and fourth fins, the fifth fin and the fourth fin are separated by a third distance, and the fifth FinFET is the second type FinFET, and further wherein the gate structure traverses the fifth fin, such that the gate structure further wraps a first portion of the fifth fin; and   a fifth epitaxy feature disposed on a second portion of the fifth fin, wherein the fifth fin is not merged with the fourth epitaxy feature and the third epitaxy feature, wherein the second contact is disposed over the fifth epitaxy feature, and further wherein the second contact spans the third distance between the fourth fin and the fifth fin.   
     
     
       101. The device of claim 100, wherein the third distance is substantially the same as the second distance. 
     
     
       102. The device of claim 100, wherein the third distance is substantially the same as the first distance. 
     
     
       103. The device of claim 100, wherein the first type FinFETs are n-type FinFETs disposed over a p-well region of a substrate and the second type FinFETs are p-type FinFETs disposed over an n-well region of the substrate. 
     
     
       104. The device of claim 100, wherein the first type FinFETs are p-type FinFETs disposed over an n-well region of a substrate and the second type FinFETs are n-type FinFETs disposed over a p-well region of the substrate. 
     
     
       105. The device of claim 100, wherein the second portions of the first, second, third, fourth, and fifth fins are source regions respectively of the first, second, third, fourth, and fifth FinFETs. 
     
     
       106. The device of claim 100, wherein the second portions of the first, second, third, fourth, and fifth fins are drain regions respectively of the first, second, third, fourth, and fifth FinFETs. 
     
     
       107. The device of claim 100, wherein the first, second, third, fourth, and fifth FinFETs are a portion of a SRAM cell. 
     
     
       108. The device of claim 107, wherein the fifth FinFET is a pull-down transistor of the SRAM cell. 
     
     
       109. The device of claim 107, wherein the fifth FinFET is a pass gate transistor of the SRAM cell. 
     
     
       110. The device of claim 107, wherein the fifth FinFET is a pull-up transistor of the SRAM cell. 
     
     
       111. The device of claim 107, wherein the first and second FinFETs are pull-up transistors of the SRAM cell and the third, fourth, and fifth FinFETs are pull-down transistors of the SRAM cell. 
     
     
       112. The device of claim 107, wherein the first and second FinFETs are pull-down transistors of the SRAM cell and the third, fourth, and fifth FinFETs are pull-up transistors of the SRAM cell. 
     
     
       113. The device of claim 100, wherein there is no fin between the fourth and the fifth fins along an entire length of the fourth and the fifth fins. 
     
     
       114. A device comprising:
 a first fin and a second fin separated by a first spacing;   a third fin, a fourth fin, and a fifth fin separated by a second spacing, wherein the fourth fin is disposed between the third fin and the fifth fin, and further wherein the second spacing is greater than the first spacing;   a first contact disposed over the first fin and the second fin, wherein the first contact spans the first spacing, a width of the first fin, and a width of the second fin, such that the first contact extends beyond outermost sidewalls of the first fin and the second fin;   a second contact disposed over the third fin, the fourth fin, and the fifth fin, wherein the second contact spans the second spacing between the third fin and the fourth fin, the second spacing between the fourth fin and the fifth fin, and a width of the fourth fin, such that the second contact does not extend beyond outermost sidewalls of the third fin and the fifth fin; and   a single gate structure that traverses the first, second, third, fourth, and fifth fins.   
     
     
       115. The device of claim 114, further comprising:
 a first isolation feature separating the first fin and the second fin, wherein top surfaces of the first fin and the second fin are lower than a top surface of the first isolation feature;   a second isolation feature separating the third fin and the fourth fin, wherein top surfaces of the third fin and the fourth fin are lower than a top surface of the second isolation feature; and   a third isolation feature separating the fourth fin and the fifth fin, wherein top surfaces of the fourth fin and the fifth fin are lower than a top surface of the third isolation feature.   
     
     
       116. The device of claim 115, further comprising:
 a first epitaxy feature disposed on a portion the first fin, a second epitaxy feature disposed on a portion of the second fin, a third epitaxy feature disposed on a portion of the third fin, a fourth epitaxy feature disposed on a portion of the fourth fin, and a fifth epitaxy feature disposed on a portion of the fifth fin;   wherein top surfaces of the first and second epitaxy features are higher than the top surface of the first isolation feature, top surfaces of the third and fourth epitaxy features are higher than the top surface of the second isolation feature, and top surfaces of the fourth and fifth epitaxy features are higher than the top surface of the third isolation feature;   wherein the first contact is disposed on the first and the second epitaxy features; and   wherein the second contact is disposed on the third, fourth, and fifth epitaxy features.   
     
     
       117. The device of claim 116, wherein the first epitaxy feature merges with the second epitaxy feature over the first isolation feature, the third epitaxy feature does not merge with the fourth epitaxy feature, and the fourth epitaxy feature does not merge with the fifth epitaxy feature. 
     
     
       118. The device of claim 117, wherein the first contact contacts a merged portion of the first epitaxy feature and the second epitaxy feature.