Output stage circuit

Abstract

An output stage circuit includes: a first transistor, including a first terminal coupled to a first node, a second terminal coupled to an output terminal, a third terminal coupled to an input terminal for receiving an input voltage, and a fourth terminal coupled to a first power terminal for receiving a first voltage; a second transistor, including a first terminal coupled to a second node, a second terminal coupled to the output terminal, a third terminal coupled to the input terminal for receiving the input voltage, and a fourth terminal coupled to ground; and a current source, coupled to the output terminal for providing a constant current.

What is claimed is: 
     
       1. An output stage circuit, comprising:
 a first transistor, comprising a first terminal coupled to a first power terminal, a second terminal coupled to an output terminal of the output stage circuit, a third terminal coupled to an input terminal for receiving an input voltage, and a fourth terminal coupled to the first power terminal for receiving a first voltage; 
 a second transistor, comprising a first terminal coupled to a second power terminal for receiving a second voltage, a second terminal coupled to the output terminal, a third terminal coupled to the input terminal for receiving the input voltage, and a fourth terminal coupled to ground; and 
 a current source, coupled to the output terminal for providing a constant current; 
 wherein the second voltage equals half the first voltage. 
 
     
     
       2. The output stage circuit of  claim 1 , wherein the second transistor is cut off when a voltage of the output terminal does not change. 
     
     
       3. The output stage circuit of  claim 1 , wherein the second transistor is turned on when a voltage of the output terminal decreases. 
     
     
       4. The output stage circuit of  claim 1 , wherein the first transistor is a P-type MOS, the first terminal of the first transistor is a source, the second terminal of the first transistor is a drain, the third terminal of the first transistor is a gate, and the fourth terminal of the first transistor is a base. 
     
     
       5. The output stage circuit of  claim 1 , wherein the second transistor is an N-type MOS, the first terminal of the second transistor is a source, the second terminal of the second transistor is a drain, the third terminal of the second transistor is a gate, and the fourth terminal of the second transistor is a base. 
     
     
       6. The output stage circuit of  claim 1 , wherein the first voltage is greater than a voltage of the output terminal and the voltage of the output terminal is greater than the second voltage. 
     
     
       7. An output stage circuit, comprising:
 a first transistor, comprising a first terminal coupled to a first power terminal for receiving a first voltage, a second terminal coupled to an output terminal of the output stage circuit, a third terminal coupled to an input terminal for receiving an input voltage, and a fourth terminal coupled to a second power terminal for receiving a second voltage; 
 a second transistor, comprising a first terminal coupled to ground, a second terminal coupled to the output terminal, a third terminal coupled to the input terminal for receiving the input voltage, and a fourth terminal coupled to ground; and 
 a current source, coupled to the output terminal for providing a constant current; 
 wherein the first voltage equals half the second voltage. 
 
     
     
       8. The output stage circuit of  claim 7 , wherein the first transistor is cut off when a voltage of the output terminal does not change. 
     
     
       9. The output stage circuit of  claim 7 , wherein the first transistor is a P-type MOS, the first terminal of the first transistor is a source, the second terminal of the first transistor is a drain, the third terminal of the first transistor is a gate, and the fourth terminal of the first transistor is a base. 
     
     
       10. The output stage circuit of  claim 7 , wherein the second transistor is an N-type MOS, the first terminal of the second transistor is a source, the second terminal of the second transistor is a drain, the third terminal of the second transistor is a gate, and the fourth terminal of the second transistor is a base. 
     
     
       11. The output stage circuit of  claim 7 , wherein the first voltage is greater than a voltage of the output terminal and the voltage of the output terminal is greater than ground. 
     
     
       12. An output stage circuit for an operational amplifier, comprising:
 a pulling-up device, comprising a first terminal coupled to a first node, a second terminal coupled to an output terminal of the output stage circuit, and a third terminal coupled to an input terminal for receiving an input voltage, wherein the pulling pulling-up device pulls up a voltage at the output terminal when the pulling-up device is conducted in response to the input voltage; 
 a pulling-down device, comprising a first terminal coupled to a second node, a second terminal coupled to the output terminal, a third terminal coupled to the input terminal for receiving the input voltage, and a fourth terminal coupled to a reference voltage, wherein the pulling-down device pulls down the voltage at the output terminal when the pulling-down device is conducted in response to the input voltage; and 
 a current source, coupled to the output terminal for providing a constant current; 
 wherein a voltage of the second terminal node is between a voltage of the first terminal node and the reference voltage. 
 
     
     
       13. The output stage circuit of  claim 12 , wherein the pulling-up device further comprises a fourth terminal coupled to a power terminal for receiving a power voltage. 
     
     
       14. An output stage circuit for an operational amplifier, comprising:
 a pulling-up device, comprising a first terminal coupled to a first node, a second terminal coupled to an output terminal of the output stage circuit, a third terminal coupled to an input terminal for receiving an input voltage, and a fourth terminal coupled to a power terminal for receiving a power voltage, wherein the pulling pulling-up device pulls up a voltage at the output terminal when the pulling-up device is conducted in response to the input voltage; 
 a pulling-down device, comprising a first terminal coupled to a second node, a second terminal coupled to the output terminal, and a third terminal coupled to the input terminal for receiving the input voltage, wherein the pulling-down device pulls down the voltage at the output terminal when the pulling-down device is conducted in response to the input voltage; and 
 a current source, coupled to the output terminal for providing a constant current; 
 wherein a voltage of the first node is between the power voltage and a voltage of the second node. 
 
     
     
       15. The output stage circuit of  claim 14 , wherein the pulling-down device further comprises a fourth terminal coupled to a reference voltage. 
     
     
       16. An output stage circuit, comprising:
 a first device, comprising a first terminal coupled to a first node, a second terminal coupled to an output terminal of the output stage circuit, and a third terminal coupled to an input terminal for receiving an input voltage;   a second device, comprising a first terminal coupled to a second node, a second terminal coupled to the output terminal, a third terminal coupled to the input terminal for receiving the input voltage, and a fourth terminal coupled to a reference voltage; and   a current source, coupled to the output terminal for providing a constant current;   wherein a voltage of the second node is between a voltage of the first node and the reference voltage.   
     
     
       17. The output stage circuit of claim 16, wherein the first device further comprises a fourth terminal coupled to a power terminal for receiving a power voltage. 
     
     
       18. The output stage circuit of claim 17, wherein the first device is a P-type MOS, the power voltage received at the fourth terminal of the first device is substantially equal to the voltage of the first node. 
     
     
       19. The output stage circuit of claim 18, wherein the voltage of the first node is a system power supply voltage. 
     
     
       20. The output stage circuit of claim 16, wherein the second device is an N-type MOS, the reference voltage coupled to the fourth terminal of the second device is a system ground. 
     
     
       21. An output stage circuit, comprising:
 a first device, comprising a first terminal coupled to a first node, a second terminal coupled to an output terminal of the output stage circuit, a third terminal coupled to an input terminal for receiving an input voltage, and a fourth terminal coupled to a power terminal for receiving a power voltage;   a second device, comprising a first terminal coupled to a second node, a second terminal coupled to the output terminal, and a third terminal coupled to the input terminal for receiving the input voltage; and   a current source, coupled to the output terminal for providing a constant current;   wherein a voltage of the first node is between the power voltage and a voltage of the second node.   
     
     
       22. The output stage circuit of claim 21, wherein the second device further comprises a fourth terminal coupled to a reference voltage. 
     
     
       23. The output stage circuit of claim 22, wherein the second device is an N-type MOS, the voltage of the second node is substantially equal to the reference voltage. 
     
     
       24. The output stage circuit of claim 23, wherein the reference voltage is a system ground. 
     
     
       25. The output stage circuit of claim 21, wherein the first device is a P-type MOS, the power voltage received at the fourth terminal of the first device is a system power supply voltage.