Stackable electronic package and method of fabricating same

Abstract

An electronic package includes a first layer having a first surface, the first layer includes a first device having a first electrical node, and a first contact pad in electrical communication with the first electrical node and positioned within the first surface. The package includes a second layer having a second surface and a third surface, the second layer includes a first conductor positioned within the second surface and a second contact pad positioned within the third surface and in electrical communication with the first conductor. A first anisotropic conducting paste (ACP) is positioned between the first contact pad and the first conductor to electrically connect the first contact pad to the first conductor such that an electrical signal may pass therebetween.

What is claimed is: 
     
       1. A method of fabricating an electronic package, the method comprising:
 forming a plurality of die package sub-layers, each sub-layer having a first surface and a second surface, wherein forming each sub-layer comprises:
 providing a device having one or more electrical nodes; 
 adhering the device to a flex layer, on a first surface of the sub-layer; 
 forming a via through the flex layer at a location adjacent each of the one or more electrical nodes; 
 forming a metallization layer that provides a direct metallic connection to each of the one or more electrical nodes, the metallization layer extending down through the via adjacent each of the one or more electrical nodes; 
 forming contact pads on the metallization layer such that the contact pads are located on the second surface of the sub-layer;  
 providing a conductor on the first surface of the sub-layer; and 
 electrically connecting the conductor to an electrical node of the device via the metallization layer, the metallization layer comprising a feed-thru extending through the flex layer to electrically connect the metallization layer to the conductor; and 
 
 compressing an anisotropic conductive paste (ACP) between the plurality of sub-layers such that the contact pad of one sub-layer is electrically connected to the conductor of an adjacent sub-layer via the ACP, wherein the ACP comprises a plurality of solder balls that conduct electrical signals. 
 
     
     
       2. The method  claim 1  wherein compressing the ACP includes compressing the ACP to have a surface area that is substantially the same as one of an area of the first surface and an area of the second surface of one of the sub-layers. 
     
     
       3. The method of  claim 1  wherein the device in each sub-layer comprises one of a memory chip, a microprocessor, a translation circuit, a buffer, a switch, a resistor, a capacitor, and an inductor. 
     
     
       4. The method of  claim 1  wherein the conductor in each sub-layer comprises copper. 
     
     
       5. The method of  claim 1  further comprising electrically connecting the plurality of die package sub-layers to a printed circuit board (PCB), with the plurality of die package sub-layers passing electrical signals to the PCB via the conductor of one of the sub-layers. 
     
     
       6. The method of  claim 5  further comprising electrically attaching the plurality of die package sub-layers to the PCB via a ball grid array (BGA). 
     
     
       7. The method of  claim 1  wherein forming each sub-layer further comprises applying an encapsulant to the first surface of the sub-layer, such that the device and the conductor are embedded in the encapsulant. 
     
     
       8. The method of  claim 7  wherein forming each sub-layer further comprises performing one of a grinding and a lapping operation to remove a portion of the encapsulant, a portion of the device, and a portion of the conductor, wherein a surface of the conductor is exposed upon performing the one of the grinding and the lapping operation. 
     
     
       9. A method of fabricating a stacked electronic package, the method comprising:
 forming at least a first sub-assembly layer and a second sub-assembly layer, wherein forming the first sub-assembly layer comprises:
 providing a device having one or more electrical nodes; 
 adhering the device to a dielectric material; 
 positioning a first conductor adjacent the device such that the first conductor is located on a first surface of the first sub-assembly layer; 
 forming a metallization layer that extends through at least one via in the dielectric material and is electrically connected with at least one of the one or more electrical nodes; and 
 forming a first contact pad on the metallization layer such that the first contact pad is located on a second surface of the first sub-assembly layer; 
   wherein forming the second sub-assembly layer comprises:
 providing a second conductor on a first surface of the second sub-assembly layer; and 
 forming a second contact pad on a second surface of the second sub-assembly layer and in electrical communication with the second conductor; and 
   positioning an electrically conducting material between and in direct contact with the contact pad of one of the first and second sub-assembly layers and with the conductor of the other of the first and second sub-assembly layers such that an electrical signal may pass therebetween.   
     
     
       10. The method of claim 9 wherein the electrically conducting material comprises one of an anisotropic conducting paste (ACP), an anisotropic conductive film (ACF), and solder. 
     
     
       11. The method of claim 9 wherein forming the metallization layer comprises:
 forming a first metallization path on the dielectric material and through the at least one via in the dielectric material;   applying a second dielectric material over the first metallization path; and   forming a second metallization path that extends through the second dielectric material to electrically connect with the first metallization path.   
     
     
       12. The method of claim 9 further comprising:
 providing a second device having one or more electrical nodes; and   adhering the second device to the dielectric material.   
     
     
       13. A stacked electronic package comprising:
 at least a first sub-assembly layer and a second sub-assembly layer, wherein the first sub-assembly layer comprises:
 a dielectric material; 
 a device coupled to the dielectric material at a first surface of the first sub-assembly layer; 
 a metallization layer extending through at least one via in the dielectric material to electrically connect with at least one electrical node of the device; 
 a first contact pad formed on the metallization layer such that the first contact pad is located on a second surface of the first sub-assembly layer; 
 a first conductor located on the first surface of the first sub-assembly layer and electrically connected to the at least one electrical node of the device via the metallization layer; and 
   wherein the second sub-assembly layer comprises:
 a second conductor positioned on a first surface of the second sub-assembly layer, and 
 a second contact pad positioned on the second surface of the second sub-assembly layer and in electrical communication with the second conductor; and 
   an electrically conducting material positioned between and in direct contact with one of the contact pad of one of the first and second sub-assembly layers and with the conductor of the other of the first and second sub-assembly layers such that an electrical signal may pass therebetween.   
     
     
       14. The stacked electronic package of claim 13 wherein the first sub-assembly layer further comprises an encapsulant partially surrounding the device and the first conductor; and
 wherein a surface of the first conductor facing away from the dielectric material is free from encapsulant.   
     
     
       15. The stacked electronic package of claim 13 wherein the electrically conducting material comprises one of an anisotropic conducting paste (ACP), an anisotropic conductive film (ACF), and solder. 
     
     
       16. The stacked electronic package of claim 13 wherein a portion of the metallization layer is sandwiched between the dielectric material and a second dielectric material. 
     
     
       17. The stacked electronic package of claim 13 further comprising a second device having one or more electrical nodes coupled to the dielectric material. 
     
     
       18. The stacked electronic package of claim 13 further comprising:
 a third sub-assembly layer comprising:
 a third conductor on a first surface of the third sub-assembly layer, and 
 a third contact pad on a second surface of the third sub-assembly layer and in electrical communication with the third conductor; and 
   an electrically conducting material positioned between the second contact pad and the third conductor such that an electrical signal may pass therebetween.   
     
     
       19. An electronic package comprising:
 a dielectric material;   a first electronic component coupled to a first side of the dielectric material;   a conductive material applied to the first side of the dielectric material adjacent the first electronic component;   a metallization path formed on a second side of the dielectric material and extending through vias therein to couple with the conductive material and the first electronic component;   a conductive pad formed on the metallization path; and   a mask layer applied on the second side of the dielectric material, the mask layer surrounding the metallization path and side surfaces of the conductive pad;   wherein a top surface of the mask layer and a top surface of the conductive pad are co-planar.   
     
     
       20. The electronic package of claim 19 wherein a bottom surface of the conductive material and a bottom surface of the first electronic component are co-planar. 
     
     
       21. The electronic package of claim 19 wherein the conductive pad comprises a gold layer stacked atop a nickel layer. 
     
     
       22. The electronic package of claim 19 wherein the first electronic component comprises a die. 
     
     
       23. The electronic package of claim 19 further comprising a second electronic component coupled to the first side of the dielectric material. 
     
     
       24. The electronic package of claim 23 wherein the metallization path comprises one of a plurality of metallization paths formed through the dielectric material; and
 wherein the plurality of metallization paths electrically couple the second electronic component to the conductive material.   
     
     
       25. The electronic package of claim 19 further comprising:
 a second electronic package comprising a metallization path forming an electrical connection between a conductive pad located on a first surface of the second electronic package and a conductive material located on a second surface of the second electronic package; and   an electrically conducting material coupling the second electronic package to the mask layer to form a stacked electronic package.   
     
     
       26. The electronic package of claim 25 wherein the electrically conducting material comprises one of an anisotropic conducting paste (ACP), an anisotropic conductive film (ACF), and solder. 
     
     
       27. The electronic package of claim 25 further comprising a third electronic package positioned adjacent the second electronic package on the mask layer, the third electronic package comprising a metallization path forming an electrical connection between a conductive pad located on a first surface of the third electronic package a conductive material located on a second surface of the third electronic package.