Nonvolatile semiconductor memory device and method for driving same

Abstract

According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and a drive circuit. The stacked body is provided on the substrate. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. A through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in an interior of the through-hole. The charge storage film is provided between the electrode film and the semiconductor pillar. The drive circuit supplies a potential to the electrode film. The diameter of the through-hole differs by a position in the stacking direction. The drive circuit supplies a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases.

The invention claimed is: 
     
       1. A nonvolatile semiconductor memory device, comprising:
 a substrate;   a stacked body provided on the substrate, the stacked body including a plurality of insulating films alternately stacked with a plurality of electrode films, a through-hole being made in the stacked body to align in a stacking direction;   a semiconductor pillar buried in an interior of the through-hole;   a charge storage film provided between the electrode film and the semiconductor pillar; and   a drive circuit supplying a potential to the electrode film,   a diameter of the through-hole differing by a position in the stacking direction,   the drive circuit supplying a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases.   
     
     
       2. The device according to  claim 1 , wherein a diameter of the through-hole decreases toward the substrate. 
     
     
       3. The device according to  claim 2 , wherein the through-holes are made collectively by dry etching. 
     
     
       4. The device according to  claim 1 , wherein
 the stacked body includes a plurality of partial stacked bodies arranged in the stacking direction, a plurality of the insulating films and a plurality of the electrode films being disposed in the partial stacked body, and   in each of the partial stacked bodies, a diameter of the through-hole decreases toward the substrate.   
     
     
       5. The device according to  claim 4 , wherein portions of the through-holes made in each of the partial stacked bodies are made collectively for the partial stacked body by dry etching. 
     
     
       6. The device according to  claim 1 , wherein
 the through-hole has a circular configuration as viewed from the stacking direction, and   a potential provided by the drive circuit to one of the electrode films is determined according to
   V=6999.4×r 3 −1971.3×r 2 +194.66×r−5.0952
 
   
       where r (μm) is a diameter of a portion of the through-hole piercing the one electrode film, V is a potential difference between the one electrode film and the semiconductor pillar, and V is a relative potential difference having a potential difference of 1 when the diameter is 0.06 μm. 
     
     
       7. The device according to  claim 1 , wherein the drive circuit includes:
 a decoder to output a control signal;   a pump circuit to increase a supplied potential; and   a switch element to switch between connecting and disconnecting the pump circuit and the electrode film based on the control signal.   
     
     
       8. The device according to  claim 7 , wherein the pump circuit and the switch element are provided for each of the electrode films. 
     
     
       9. The device according to  claim 1 , further comprising:
 a back gate disposed between the substrate and the stacked body; and   a connection member provided in the back gate to connect two adjacent semiconductor pillars to each other.   
     
     
       10. The device according to  claim 1 , wherein a memory cell region and a peripheral circuit region are set in the substrate, the semiconductor pillar and the charge storage film are disposed in the memory cell region, and the drive circuit is disposed in the peripheral circuit region. 
     
     
       11. A method for driving a nonvolatile semiconductor memory device, the device including: a substrate; a stacked body provided on the substrate, the stacked body including a plurality of insulating films alternately stacked with a plurality of electrode films, a through-hole being made in the stacked body to align in a stacking direction; a semiconductor pillar buried in an interior of the through-hole; and a charge storage film provided between the electrode film and the semiconductor pillar, a diameter of the through-hole differing by a position in the stacking direction, the method comprising:
 when applying a potential to the electrode film, supplying a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases.   
     
     
       12. The method according to  claim 11 , comprising providing a potential to one of the electrode films, the potential being determined according to
   V=6999.4×r 3 −1971.3×r 2 +194.66×r−5.0952
   
       where r (μm) is a diameter of a portion of the through-hole piercing the one electrode film, V is a potential difference between the one electrode film and the semiconductor pillar, and V is a relative potential difference having a potential difference of 1 when the diameter is 0.06 μm,
 the through-hole having a circular configuration as viewed from the stacking direction. 
 
     
     
       13. The method according to  claim 11 , wherein the potential is a writing potential to inject an electron from the semiconductor pillar into the charge storage film. 
     
     
       14. The method according to  claim 11 , wherein the potential is a reading potential to detect whether or not an electron is stored in the charge storage film. 
     
     
       15. A nonvolatile semiconductor memory device comprising:
 a semiconductor substrate;   a source line provided above the semiconductor substrate;   a bit line provided above the source line;   a memory string including
 a first selection transistor connected to the bit line, 
 a second selection transistor connected to the source line, and 
 a plurality of electrically-series-connected memory transistors connected between the first selection transistor and the second selection transistor, the memory transistors including
 a first memory cell transistor being above the semiconductor substrate, 
 a second memory cell transistor being above the first memory cell transistor, and 
 a third memory cell transistor being above the second memory cell transistor; 
 
 a first word line being above the semiconductor substrate and electrically connected to a gate of the first memory cell transistor; 
 a second word line being above the first word line and electrically connected to a gate of the second memory cell transistor; 
 a third word line being above the second word line and electrically connected to a gate of the third memory cell transistor; 
 a driver circuit configured to apply voltages to the first to third word lines, respectively; and 
 a control circuit configured to perform a read operation on a condition that
 the driver circuit applies a second voltage to the second word line and applies a third voltage which is higher than the second voltage to the third word line when a read operation for the first memory cell transistor is performed, 
 the driver circuit applies a first voltage which is lower than the second voltage to the first word line and applies the third voltage to the third word line when a read operation for the second memory cell transistor is performed, and 
 the driver circuit applies the first voltage to the first word line and applies the second voltage to the second word line when a read operation for the third memory cell transistor is performed.  
 
   
     
     
       16. The device according to claim 15, further comprising:
 a fourth memory cell transistor being above the third memory cell transistor; and   a fourth word line electrically connected to a gate of the fourth memory cell transistor,   wherein the control circuit is configured to perform a read operation on a condition that a fourth voltage is applied to the fourth word line when the read operation for the first memory cell transistor is performed, when the read operation for the second memory cell transistor is performed and when the read operation for the third memory cell transistor is performed,   the third voltage is lower than the fourth voltage.    
     
     
       17. The device according to claim 15, wherein the first memory cell transistor includes a first portion of a semiconductor body, the second memory cell transistor includes a second portion of the semiconductor body, the third memory cell transistor includes a third portion of the semiconductor body, a first diameter of the first portion is smaller than a second diameter of the second portion, and the second diameter is smaller than a third diameter of the third portion.  
     
     
       18. The device according to claim 15, wherein
 the driver circuit includes:
 a pump circuit unit configured to apply voltages to the first to third word lines, respectively, and 
 a switch circuit unit connected between the pump circuit unit and the first to third word lines and configured to transfer the voltages applied from the pump circuit unit to the first to third word lines, respectively; and 
   the control circuit is configured to perform a read operation on a condition that
 the pump circuit unit applies a second voltage and a third voltage to the switch circuit unit and the switch circuit unit transfers the second voltage and the third voltage to the second word line and the third word line, respectively, when a read operation for the first memory cell transistor is performed, 
 the pump circuit unit applies a first voltage and the third voltage to the switch circuit unit and the switch circuit unit transfers the first voltage and the third voltage to the first word line and the third word line, respectively, when a read operation for the second memory cell transistor is performed, and 
 the pump circuit unit applies the first voltage and the second voltage to the switch circuit unit and the switch circuit unit transfers the first voltage and the second voltage to the first word line and the second word line, respectively, when a read operation for the third memory cell transistor is performed.  
   
     
     
       19. A nonvolatile semiconductor memory device, comprising:
 a substrate;   a first electrode film provided on the substrate, the first electrode film being spaced from the substrate;   a second electrode film provided on the first electrode film, the second electrode film being positioned above and spaced from the first electrode film;   a third electrode film provided on the second electrode film, the third electrode film being positioned above and spaced from the second electrode film;   a semiconductor pillar intersecting the first electrode film, the second electrode film and the third electrode film, a first portion of the semiconductor pillar being disposed in the first electrode film, a second portion of the semiconductor pillar being disposed in the second electrode film and a third portion of the semiconductor pillar being disposed in the third electrode film, a first diameter of the first portion being smaller than a second diameter of the second portion, and the second diameter being smaller than a third diameter of the third portion;   a bit line connected to the semiconductor pillar above the third electrode film;   a charge storage film provided between the semiconductor pillar and the first electrode film, between the semiconductor pillar and the second electrode film and between the semiconductor pillar and the third electrode film; and   a drive circuit supplying a first potential to the first electrode film, supplying a second potential to the second electrode film and supplying a third potential to the third electrode film, the first potential being lower than the second potential, and the second potential being lower than the third potential.    
     
     
       20. The device according to claim 19, further comprising a fourth electrode film provided on the third electrode film, the fourth electrode film being spaced from the third electrode film,
 the semiconductor pillar intersecting the fourth electrode film,   a fourth portion of the semiconductor pillar being disposed in the fourth electrode film,   the third diameter being smaller than a fourth diameter of the fourth portion,   the drive circuit supplying a fourth potential to the fourth electrode film, the third potential being lower than the fourth potential.    
     
     
       21. The device according to claim 19, wherein the drive circuit includes:
 a decoder to output a control signal;   a pump circuit to increase a supplied potential; and   a switch element to switch between connecting and disconnecting the pump circuit and one of the first electrode film, the second electrode film and the third electrode film based on the control signal.    
     
     
       22. A method for driving a nonvolatile semiconductor memory device, the device including: a first memory cell transistor being above a semiconductor substrate; a second memory cell transistor being above the first memory cell transistor; a third memory cell transistor being above the second memory cell transistor; a first word line electrically connected to a gate of the first memory cell transistor; a second word line electrically connected to a gate of the second memory cell transistor; a third word line electrically connected to a gate of the third memory cell transistor, a bit line; a source line; a first selection transistor connected to the bit line; a second selection transistor connected to the source line; the first to third memory cell transistors connected between the first and second selection transistors; the first selection transistor being above the third memory cell transistor; and a driver circuit, the method comprising using the driver circuit to:
 apply a second voltage to the second word line and apply a third voltage to the third word line when a read operation for the first memory cell transistor is performed;   apply a first voltage to the first word line and apply the third voltage to the third word line when a read operation for the second memory cell transistor is performed; and   apply the first voltage to the first word line and apply the second voltage to the second word line when a read operation for the third memory cell transistor is performed,   wherein the first voltage is lower than the second voltage, and the second voltage is lower than the third voltage.    
     
     
       23. The method according to claim 22, the device further including: a fourth memory cell transistor being above the third memory cell transistor; and a fourth word line electrically connected to a gate of the fourth memory cell transistor,
 the method further comprising:   applying a fourth voltage to the fourth word line when the read operation for the first memory cell transistor is performed, when the read operation for the second memory cell transistor is performed and when the read operation for the third memory cell transistor is performed,   wherein the third voltage is lower than the fourth voltage.    
     
     
       24. The method according to claim 22, wherein the first memory cell transistor includes a first portion of a semiconductor body, the second memory cell transistor includes a second portion of the semiconductor body, the third memory cell transistor includes a third portion of the semiconductor body, a first diameter of the first portion is smaller than a second diameter of the second portion, and the second diameter is smaller than a third diameter of the third portion.