Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices

Abstract

A method for fabricating a low resistance, low inductance device for high current semiconductor flip-chip products. A structure is produced, which comprises a semiconductor chip with metallization traces, copper lines in contact with the traces, and copper bumps located in an orderly and repetitive arrangement on each line so that the bumps of one line are positioned about midway between the corresponding bumps of the neighboring lines. A substrate is provided which has elongated copper leads with first and second surfaces, the leads oriented at right angles to the lines. The first surface of each lead is connected to the corresponding bumps of alternating lines using solder elements. Finally, the assembly is encapsulated in molding compound so that the second lead surfaces remain un-encapsulated.

We claim: 
     
       1. A method for fabricating a low resistance, low inductance interconnection structure for high current semiconductor flip-chip products, comprising the steps of:
 providing a semiconductor wafer having metallization traces, the wafer surface protected by an overcoat, and windows in the overcoat to expose portions of the metallization traces;   forming copper lines on the overcoat, contacting the traces by filling the windows with metal;   depositing a layer of photo-imageable insulation material over the lines and the remaining wafer surface;   opening windows in the insulation material to expose portions of the lines, the locations of the windows selected in an orderly and repetitive arrangement on each line so that the windows of one line are positioned about midway between the corresponding windows of the neighboring lines; and   forming copper bumps in the windows, in contact with the lines.   
     
     
       2. The method according to  claim 1  further comprising the step of depositing a cap of solderable metal layers on each bump. 
     
     
       3. The method according to  claim 1  wherein the number and locations of the windows in the overcoat are selected as needed for the devices employing the metallization traces. 
     
     
       4. The method according to  claim 1  wherein the copper lines are oriented parallel to the metallization traces. 
     
     
       5. The method according to  claim 1  wherein the copper lines are oriented at right angles to the metallization traces. 
     
     
       6. The method according to  claim 1  wherein the step of forming copper lines comprises the steps of:
 depositing a barrier metal layer over the wafer surface; 
 depositing a seed metal layer over the barrier metal layer; 
 depositing a first photoresist layer over the seed metal layer in a height commensurate with the height of intended copper lines; 
 opening windows in the photoresist layer so that the windows are shaped as the intended lines; 
 depositing copper to fill the photoresist windows and form copper lines; 
 removing the first photoresist layer; and 
 removing the portions of the adhesion and barrier layers, which are exposed after removing the first photoresist layer. 
 
     
     
       7. The method according to  claim 6 , wherein the step of depositing copper comprises an electroplating technique. 
     
     
       8. The method according to  claim 1  wherein the step of forming copper bumps comprises the steps of:
 depositing a barrier metal layer over the wafer surface; 
 depositing a seed metal layer over the barrier metal layer; 
 depositing a second photoresist layer over the seed metal layer in a height commensurate with the height of the intended copper bumps; 
 opening windows in the photoresist layer in locations intended for copper bumps, and of a width commensurate with the width of the intended copper bumps; 
 filling the photoresist windows by depositing copper to form copper bumps; 
 removing the second photoresist layer; and 
 removing the portions of the adhesion and barrier layers, which are exposed after removing the second photoresist layer. 
 
     
     
       9. The method according the step  8 , wherein the step of depositing copper comprises an electroplating technique. 
     
     
       10. The method according to  claim 8  further comprising the step of:
 depositing one or more solderable metal layers on the surface of the copper bump, before removing the second photoresist layer. 
 
     
     
       11. The method according to  claim 10  wherein said solderable metal layers include a layer of nickel on the copper surface, followed by a layer of palladium on the nickel layer. 
     
     
       12. A method for fabricating a low resistance, low inductance interconnection device for high current semiconductor flip-chip products, comprising the steps of:
 providing a structure comprising a semiconductor chip having metallization traces, copper lines in contact with the traces, and copper bumps located in an orderly and repetitive arrangement on each line so that the bumps of one line are positioned about midway between the corresponding bumps of the neighboring lines;   providing a substrate having elongated copper leads with first and second surfaces, the leads oriented at right angles to the lines;   connecting the first surface of each lead to the corresponding bumps of alternating lines using solder elements; and   encapsulating the assembly in molding compound so that the second lead surfaces remain un-encapsulated.   
     
     
       13. The method according to  claim 12  wherein the substrate is a leadframe including copper. 
     
     
       14. A method for fabricating a low resistance, low inductance interconnection system for high current semiconductor flip-chip devices, comprising the steps of:
 providing a low resistance, low inductance interconnection device comprising:
 a semiconductor chip structure including copper lines in contact with chip metallization traces, and copper bumps located in an orderly and repetitive arrangement on each line, the bumps of one line positioned about midway between the corresponding bumps of the neighboring lines; 
 a substrate having elongated copper leads with first and second surfaces, the leads at right angles to the lines, the first lead surfaces connected to the corresponding bumps of alternating lines by solder elements; and 
 the chip structure and substrate encapsulated so that the second lead surfaces remain un-encapsulated; 
   providing a circuit board having copper contact pads parallel to the leads; and   attaching the second surface of the device leads to the board pads using solder layers.   
     
     
       15. A method comprising the steps of:
 providing a structure comprising a semiconductor chip having metallization traces, a protective overcoat layer formed above the metallization traces, first windows formed in the protective overcoat exposing portions of the metallization traces, conductive lines formed over the overcoat layer and in electrical contact with the metallization traces through the first windows, an insulating layer formed over and between the conductive lines, the insulating layer having a first thickness between the conductive lines and a second thickness over the conductive lines, second windows in the insulating layer exposing portions of the conductive lines, and one or more metal bumps contacting each conductive line through the second windows in the insulating layer;   providing a substrate having conductive leads with first and second surfaces;   connecting the first surface of each conductive lead to a metal bump on at least one of said conductive lines using conductive elements such that the second surface of each conductive lead is facing away from said connected metal bump;   and at least partially encapsulating the assembly in molding compound so that the second lead surfaces of the conductive leads remain un-encapsulated by the molding compound and available for further electrical attachment.   
     
     
       16. The method according to claim 15 wherein the protective overcoat layer is 0.7 to 1.5 μm thick. 
     
     
       17. The method according to claim 15 wherein the second thickness of the insulating layer is less than the first thickness. 
     
     
       18. The method according to claim 17 wherein the step of at least partially encapsulating the assembly comprises submitting the assembly to a block mold, in which a plurality of assembly units are encapsulated in a batch molding process, and singulating the assembly such that the sidewalls of the encapsulated assembly are straight. 
     
     
       19. The method according to claim 15 wherein the first thickness of the insulating layer is 10 to 20 μm. 
     
     
       20. The method according to claim 15 wherein the substrate is a metallic leadframe. 
     
     
       21. The method according to claim 15 wherein the step of at least partially encapsulating the assembly comprises submitting the assembly to a block mold, in which a plurality of assembly units are encapsulated in a batch molding process, and singulating the assembly such that the sidewalls of the encapsulated assembly are straight. 
     
     
       22. The method according to claim 15 wherein the conductive lines comprise electroplated copper or copper alloys. 
     
     
       23. The method according to claim 15 wherein the conductive lines comprise silver or silver alloys. 
     
     
       24. The method according to claim 15 wherein the conductive lines comprise carbon nano-tubes. 
     
     
       25. An assembly comprising:
 a semiconductor chip having metallization traces, a protective overcoat layer formed above the metallization traces, first windows formed in the protective overcoat exposing portions of the metallization traces, conductive lines formed over the overcoat layer and in electrical contact with the metallization traces through the first windows, an insulating layer formed over and between the conductive lines, the insulating layer having a first thickness between the conductive lines and a second thickness over the conductive lines, second windows in the insulating layer exposing portions of the conductive lines, and one or more metal bumps contacting each conductive line through the second windows in the insulating layer;   a substrate having conductive leads with first and second surfaces, each conductive lead having a first surface connected to a metal bump on at least one of said conductive lines using conductive elements and a second surface facing away from said connected metal bump;   and a molding compound at least partially encapsulating the assembly so that the second lead surfaces of the conductive leads remain un-encapsulated by the molding compound and available for further electrical attachment.   
     
     
       26. The assembly of claim 25 wherein the protective overcoat layer is 0.7 to 1.5 μm thick. 
     
     
       27. The assembly of claim 25 wherein the second thickness of the insulating layer is less than the first thickness. 
     
     
       28. The assembly of claim 27 wherein the molding compound at least partially encapsulating the assembly is formed by submitting the assembly to a block mold, in which a plurality of assembly units are encapsulated in a batch molding process, and singulating the assembly such that the sidewalls of the mold compound encapsulating the assembly are straight. 
     
     
       29. The assembly of claim 25 wherein the first thickness of the insulating layer is 10 to 20 μm. 
     
     
       30. The assembly of claim 25 wherein the substrate is a metallic leadframe. 
     
     
       31. The assembly of claim 25 wherein the molding compound at least partially encapsulating the assembly is formed by submitting the assembly to a block mold, in which a plurality of assembly units are encapsulated in a batch molding process, and singulating the assembly such that the sidewalls of the mold compound encapsulating the assembly are straight. 
     
     
       32. The assembly of claim 25 wherein the conductive lines comprise electroplated copper or copper alloys. 
     
     
       33. The assembly of claim 25 wherein the conductive lines comprise silver or silver alloys. 
     
     
       34. The assembly of claim 25 wherein the conductive lines comprise carbon nanotubes.