Three-dimensional nonvolatile memory cell structure with upper body connection

Abstract

A three-dimensional integrated circuit non-volatile memory array includes a memory array of vertical channel NAND flash strings connected between a substrate source line and upper layer connection lines which each include n-type drain regions and p-type body line contact regions alternately disposed on each side of undoped or lightly doped string body regions so that each NAND flash string includes a vertical string body portion connected to a horizontal string body portion formed from the string body regions of the upper body connection lines.

What is claimed is: 
     
       1. A non-volatile memory device, comprising:
 a substrate comprising a source line region of a first conductivity type formed at a surface of the substrate; and   a NAND flash memory array formed over the substrate comprising a plurality of NAND flash strings, each comprising a vertical channel string body connected between the source line region and an upper semiconductor layer which extends parallel to the surface of the substrate, where the upper semiconductor layer comprises:
 a horizontal string body region connected to each vertical channel string body, 
 a drain region of the first conductivity type connected to each horizontal string body region, and 
 a body line contact region of a second, opposite conductivity type connected to each horizontal string body region. 
   
     
     
       2. The non-volatile memory device of  claim 1 , where the source line region comprises a heavily doped N+ source line region formed in the substrate. 
     
     
       3. The non-volatile memory device of  claim 1 , where each NAND flash string comprises a plurality of series-connected transistors formed along a corresponding vertical channel string body between the source line region and the upper semiconductor layer, comprising an upper select gate transistor, a lower select gate transistor, and a plurality of memory cell transistors formed between the upper and lower select gate transistors. 
     
     
       4. The non-volatile memory device of  claim 3 , where the upper select gate transistor has a first channel portion that runs parallel to the surface of the substrate and a second channel portion that runs perpendicular to the surface of the substrate. 
     
     
       5. The non-volatile memory device of  claim 4 , where the upper select gate transistor comprises a gate electrode that is located between the first channel portion of the upper select gate transistor and the surface of the substrate. 
     
     
       6. The non-volatile memory device of  claim 3 , where upper select gate transistor comprises a string select transistor formed adjacent to a corresponding horizontal string body region that is connected to the vertical channel string body, thereby defining horizontal and vertical string body portions for the NAND flash string. 
     
     
       7. The non-volatile memory device of  claim 1 , where the NAND flash memory array comprises a plurality of upper semiconductor layer strips running in a bit line direction which are electrically isolated from one another in a word line direction, each upper semiconductor layer strip electrically connecting a shared bit line through one or more drain regions in said upper semiconductor layer strip to NAND flash strings from different word lines. 
     
     
       8. The non-volatile memory device of  claim 7 , where the plurality of upper semiconductor layer strips electrically connect a shared body line through body line contact regions in said upper semiconductor layer strips to NAND flash strings sharing one or more common word lines. 
     
     
       9. The non-volatile memory device of  claim 1 , where the upper semiconductor layer comprises alternating first and second connection strips running in the bit line direction and formed in a continuous semiconductor layer,
 where each first connection strip is formed over a column of NAND flash strings and comprises a horizontal string body region connected to each underlying NAND flash string, and a drain region connected to each horizontal string body region for electrically connecting a bit line through said drain region and horizontal string body region to said underlying NAND flash string; and   where each second connection strip is formed adjacent to a corresponding first connection strip and comprises a body line contact region connected to each horizontal string body region in the corresponding first connection strip for electrically connecting a body line through said body line contact region and each connected horizontal string body region to said underlying NAND flash string.   
     
     
       10. The non-volatile memory device of  claim 9 , where the upper semiconductor layer comprises a plurality of first connection strips formed over a corresponding plurality of NAND flash string columns running in a bit line direction, and a plurality of second connection strips formed between the plurality of first connection strips for electrically connecting one or more shared body line conductors through body line contact regions formed in each second connection strip to the plurality of NAND flash strings. 
     
     
       11. The non-volatile memory device of  claim 1 , where the drain region comprises an n+ doped region formed in the upper semiconductor layer to be laterally offset from the vertical channel string body, and where the body line contact region comprises a p+ doped region formed in the upper semiconductor layer to be laterally offset from the vertical channel string body. 
     
     
       12. A NAND Flash memory cell array formed on a substrate comprising a plurality of semiconductor string bodies running in a direction perpendicular to a surface of the substrate, where each semiconductor string body is connected between an n-type source region formed in the substrate and an upper semiconductor layer formed over the substrate, where each upper semiconductor layer comprises:
 a horizontal string body region connected to and formed over an associated semiconductor string body,   an n-type conductivity region connected through each horizontal string body region to the associated semiconductor string body, and   a p-type conductivity region connected through each horizontal string body region to the associated semiconductor string body,   where the n-type conductivity region and p-type conductivity region are each laterally offset from the associated semiconductor string body.   
     
     
       13. The NAND Flash memory cell array of  claim 12 , further comprising an upper select gate formed at an upper end of each semiconductor string body, each of said upper select gates controlling a first channel portion formed in the horizontal string body region that runs parallel to the surface of the substrate and a second channel portion formed in the semiconductor string body that runs perpendicular to the surface of the substrate. 
     
     
       14. The NAND Flash memory cell array of  claim 13 , where the upper select gate is located between the first channel portion and the surface of the substrate. 
     
     
       15. The NAND Flash memory cell array of  claim 13 , wherein each upper select gate is positioned upon application of a first voltage to induce n-type conductivity in the first and second channel portions to electrically connect the first channel portion to an associated n-type conductivity region in the upper semiconductor layer. 
     
     
       16. The NAND Flash memory cell array of  claim 13 , wherein each upper select gate is positioned upon application of a second voltage to induce p-type conductivity in the first and second channel portions to electrically connect the first channel portion to an associated p-type conductivity region in the upper semiconductor layer. 
     
     
       17. The NAND Flash memory cell array of  claim 12 , where each n-type conductivity region is electrically connected to a first conductive line, and where each p-type conductivity connective region is electrically connected to a second conductive line. 
     
     
       18. The NAND Flash memory cell array of  claim 17 , wherein said first conductive line comprises a bit line for transferring data bits to or from one or more semiconductor string bodies, and wherein said second conductive line comprises a body line for transferring a positive voltage to one or more semiconductor string bodies. 
     
     
       19. A method for reading an addressed memory cell transistor from a plurality of NAND flash strings, each comprising a vertical channel string body in which a plurality of series-connected transistors are formed between a substrate source line region and an upper semiconductor layer, the plurality of series-connected transistors comprising an upper select gate transistor, a lower select gate transistor, and a plurality of memory cell transistors formed between the upper and lower select gate transistors, comprising:
 applying a bit line read voltage to a bit line conductor which is connected through an n-type string drain region formed in the upper semiconductor layer to a selected flash string on which the addressed memory cell transistor is formed;   applying a body voltage to a body line conductor which is connected through a p-type string region formed in the upper semiconductor layer to the selected flash string on which the addressed memory cell transistor is formed; and   applying a read gate voltage to the addressed memory cell transistor while otherwise applying a positive gate voltage to the other series-connected transistors formed on the selected flash string, thereby reading a value from the addressed memory cell transistor that is transferred through the n-type string drain region formed in the upper semiconductor layer and to the bit line conductor under control of the upper select gate transistor for the selected flash string.   
     
     
       20. The method of  claim 19 , where applying the positive gate voltage to the other series-connected transistors comprises applying the positive gate voltage to an upper select gate formed at an upper end of the selected flash string to control a first channel portion of a horizontal string body region formed in the upper semiconductor layer and a second channel portion of a vertical string body formed in the selected flash string. 
     
     
       21. A method for erasing an erase block of NAND flash strings, each comprising a vertical channel string body in which a plurality of series-connected transistors are formed between a substrate source line region and an upper semiconductor layer, the plurality of series-connected transistors comprising an upper select gate transistor, a lower select gate transistor, and a plurality of memory cell transistors formed between the upper and lower select gate transistors, comprising:
 applying a large positive erase voltage to a body line conductor which is connected through p-type string regions formed in the upper semiconductor layer to the erase block of NAND flash strings, thereby charging the vertical channel string bodies in the erase block of NAND flash strings;   applying a smaller erase gate voltage to the plurality of series-connected transistors formed on the erase block of NAND flash strings; and   floating the substrate source line and one or more bit line conductors which are connected through an n-type string drain regions formed in the upper semiconductor layer to the erase block of NAND flash strings.   
     
     
       22. A vertical channel NAND Flash memory device, comprising:
 a substrate;   a plurality of word lines, each word line extending in a first direction;   a plurality of bit lines, each bit line extending in a second direction perpendicular to the first direction;   a plurality of vertical pillars extending in a third direction that is perpendicular to both the first direction and the second direction, each vertical pillar comprising a plurality of memory cells and penetrating through multiple word lines, and each vertical pillar comprising a vertical tube comprising polysilicon material,
 each vertical tube surrounding a pillar core made of dielectric material; 
 each vertical tube being surrounded by a multilayered memory film at a first location, the multilayered memory film being surrounded by and in contact with a first transistor gate, the multilayered memory film comprising a tunnel dielectric, a charge storage layer, and a coupling dielectric, 
 each vertical tube being surrounded by a gate dielectric at a second location, the gate dielectric being surrounded by and in contact with a second transistor gate, 
 the plurality of vertical pillars comprising a first group of vertical pillars arranged in the second direction; and 
   a first connection layer comprising semiconductor material separate from the substrate and connecting to an end portion of each vertical tube belonging to the first group of vertical pillars, such that the polysilicon material of each vertical tube belonging to the first group of vertical pillars directly connects to semiconductor material of the first connection layer, the first connection layer being electrically connected to at least a body line comprising metal and a first via contacting the first connection layer, the body line and the first connection layer configured to be connected to a positive erase voltage during an erase operation.   
     
     
       23. The vertical channel NAND Flash memory device of claim 22, further comprising:
 a second connection layer, the first connection layer and the second connection layer each extending in the second direction and being spaced apart from each other on a same plane formed by the first direction and the second direction,   wherein the plurality of vertical pillars further comprises a second group of vertical pillars arranged in the second direction,   wherein the second connection layer comprises polysilicon material and is connected to an end portion of each vertical tube belonging to the second group of vertical pillars, such that the polysilicon material of each vertical tube belonging to the second group of vertical pillars directly connects to the polysilicon material of the second connection layer, the first connection layer and the second connection layer being electrically connected to each other through at least the body line, the first via and a second via, and   wherein the second connection layer is configured to be connected to the positive erase voltage during the erase operation.   
     
     
       24. The vertical channel NAND Flash memory device of claim 23, wherein the first group of pillars and the second group of pillars each comprise at least four vertical pillars arranged in a straight line in the second direction, the first connection layer and the second connection layer further being arranged side by side, and the body line extends in the first direction. 
     
     
       25. The vertical channel NAND Flash memory device of claim 23, wherein the substrate connects to each vertical pillar of the first group of pillars and the second group of pillars, the substrate connection of each vertical pillar being at a far side from the end portion of each vertical pillar. 
     
     
       26. The vertical channel NAND Flash memory device of claim 22, wherein the first connection layer connects to a matrix of vertical pillars such that the first group of vertical pillars comprises at least four vertical pillars, and a second group of vertical pillars of the plurality of vertical pillars are arranged in a straight line in the first direction, and
 wherein the first connection layer connects to an end portion of each vertical tube belonging to the second group of vertical pillars, such that the polysilicon material of each vertical tube belonging to the second group of vertical pillars directly connects to the polysilicon material of the first connection layer, and wherein the first connection layer comprises an N-type doped region.   
     
     
       27. The vertical channel NAND Flash memory device of claim 22, wherein the first connection layer and the second connection layer each comprise an N+ region. 
     
     
       28. The vertical channel NAND Flash memory device of claim 27, wherein each word line of the plurality of word lines comprises polysilicon material. 
     
     
       29. The vertical channel NAND Flash memory device of claim 22, wherein the first connection layer and the second connection layer each comprise a P+ region. 
     
     
       30. The vertical channel NAND Flash memory device of claim 22, wherein each memory cell of the plurality of memory cells is a floating gate memory cell. 
     
     
       31. The vertical channel NAND Flash memory device of claim 22, wherein each memory cell of the plurality of memory cells comprises the charge storage layer with charge trapping material. 
     
     
       32. The vertical channel NAND Flash memory device of claim 22, wherein the charge storage layer comprises silicon nitride.