Nonvolatile semiconductor memory device and method for driving same

Abstract

According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and a drive circuit. The stacked body is provided on the substrate. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. A through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in an interior of the through-hole. The charge storage film is provided between the electrode film and the semiconductor pillar. The drive circuit supplies a potential to the electrode film. The diameter of the through-hole differs by a position in the stacking direction. The drive circuit supplies a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases.

The invention claimed is: 
     
       1. A nonvolatile semiconductor memory device, comprising:
 a substrate;   a stacked body provided on the substrate, the stacked body including a plurality of insulating films alternately stacked with a plurality of electrode films, a through-hole being made in the stacked body to align in a stacking direction;   a semiconductor pillar buried in an interior of the through-hole;   a charge storage film provided between the electrode film and the semiconductor pillar; and   a drive circuit supplying a potential to the electrode film,   a diameter of the through-hole differing by a position in the stacking direction,   the drive circuit supplying a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases.   
     
     
       2. The device according to  claim 1 , wherein a diameter of the through-hole decreases toward the substrate. 
     
     
       3. The device according to  claim 2 , wherein the through-holes are made collectively by dry etching. 
     
     
       4. The device according to  claim 1 , wherein
 the stacked body includes a plurality of partial stacked bodies arranged in the stacking direction, a plurality of the insulating films and a plurality of the electrode films being disposed in the partial stacked body, and   in each of the partial stacked bodies, a diameter of the through-hole decreases toward the substrate.   
     
     
       5. The device according to  claim 4 , wherein portions of the through-holes made in each of the partial stacked bodies are made collectively for the partial stacked body by dry etching. 
     
     
       6. The device according to  claim 1 , wherein
 the through-hole has a circular configuration as viewed from the stacking direction, and   a potential provided by the drive circuit to one of the electrode films is determined according to
   V=6999.4×r 3 −1971.3×r 2 +194.66×r−5.0952
 
   
       where r (μm) is a diameter of a portion of the through-hole piercing the one electrode film, V is a potential difference between the one electrode film and the semiconductor pillar, and V is a relative potential difference having a potential difference of 1 when the diameter is 0.06 μm. 
     
     
       7. The device according to  claim 1 , wherein the drive circuit includes:
 a decoder to output a control signal;   a pump circuit to increase a supplied potential; and   a switch element to switch between connecting and disconnetting the pump circuit and the electrode film based on the control signal.   
     
     
       8. The device according to  claim 7 , wherein the pump circuit and the switch element are provided for each of the electrode films. 
     
     
       9. The device according to  claim 1 , further comprising:
 a back gate disposed between the substrate and the stacked body; and   a connection member provided in the back gate to connect two adjacent semiconductor pillars to each other.   
     
     
       10. The device according to  claim 1 , wherein a memory cell region and a peripheral circuit region are set in the substrate, the semiconductor pillar and the charge storage film are disposed in the memory cell region, and the drive circuit is disposed in the peripheral circuit region. 
     
     
       11. A method for driving a nonvolatile semiconductor memory device, the device including: a substrate; a stacked body provided on the substrate, the stacked body including a plurality of insulating films alternately stacked with a plurality of electrode films, a through-hole being made in the stacked body to align in a stacking direction; a semiconductor pillar buried in an interior of the through-hole; and a charge storage film provided between the electrode film and the semiconductor pillar, a diameter of the through-hole differing by a position in the stacking direction, the method comprising:
 when applying a potential to the electrode film, supplying a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases.   
     
     
       12. The method according to  claim 11 , comprising providing a potential to one of the electrode films, the potential being determined according t
   V=6999.4×r 3 −1971.3×r 2 +194.66×r−5.0952
   
       where r (μm) is a diameter of a portion of the through-hole piercing the one electrode film, V is a potential difference between the one electrode film and the semiconductor pillar, and V is a relative potential difference having a potential difference of 1 when the diameter is 0.06 μm,
 the through-hole having a circular configuration as viewed from the stacking direction. 
 
     
     
       13. The method according to  claim 11 , wherein the potential is a writing potential to inject an electron from the semiconductor pillar into the charge storage film. 
     
     
       14. The method according to  claim 11 , wherein the potential is a reading potential to detect whether or not an electron is stored in the charge storage film. 
     
     
       15. A nonvolatile semiconductor memory device comprising:
 a semiconductor substrate having a surface extending in a first direction and a second direction crossing the first direction;   a plurality of series-connected memory cell transistors, the memory cell transistors including
 a first memory cell transistor being provided at one side of the semiconductor substrate in a third direction crossing the first direction and the second direction 
 a second memory cell transistor being provided at one side of the first memory cell transistor in the third direction, 
 a third memory cell transistor being provided at one side of the second memory cell transistor in the third direction, and 
 a fourth memory cell transistor being provided at one side of the third memory cell transistor in the third direction; 
   a plurality of control electrodes being stacked in the third direction, and each extending in the first direction and the second direction, the control electrodes including
 a first control electrode connected to a gate of the first memory cell transistor, 
 a second control electrode connected to a gate of the second memory cell transistor, 
 a third control electrode connected to a gate of the third memory cell transistor, and 
 a fourth control electrode connected to a gate of the fourth memory cell transistor, 
   a plurality of switch elements having one ends connected to the control electrodes, respectively;   a plurality of electric lines having one ends connected to other ends of the switch elements, respectively; and   a driver circuit being connected to the electric lines, the driver circuit including
 a first pump circuit being configured to generate a first voltage to be supplied on the first control electrode when a read operation to the second memory cell transistor is performed, 
 a second pump circuit being configured to generate a second voltage to be supplied on the second control electrode when the read operation to the second memory cell transistor is performed, 
 a third pump circuit being configured to generate a third voltage to be supplied on the third control electrode when the read operation to the second memory cell transistor is performed, and 
 a fourth pump circuit being configured to generate a fourth voltage to be supplied on the fourth control electrode when the read operation to the second memory cell transistor is performed, 
   wherein   the first voltage is higher than the second voltage,   the third voltage is higher than the first voltage and the second voltage, and   the fourth voltage is higher than the third voltage.    
     
     
       16. The device according to claim 15, wherein
 when a read operation to the third memory cell transistor is performed
 the first pump circuit being configured to generate the first voltage, 
 the second pump circuit being configured to generate a fifth voltage, 
 the third pump circuit being configured to generate a sixth voltage, and 
 the fourth pump circuit being configured to generate the fourth voltage, and 
 the fifth voltage is higher than the first voltage, 
 the fifth voltage is higher than the sixth voltage, and 
 the fourth voltage is higher than the first voltage and the third voltage.  
   
     
     
       17. The device according to claim 16, wherein
 the memory cell transistors further including
 a fifth memory cell transistor being provided at the one side of the semiconductor substrate in the third direction, 
 a sixth memory cell transistor being provided at one side of the fifth memory cell transistor in the third direction, 
 a seventh memory cell transistor being provided at one side of the sixth memory cell transistor in the third direction, and 
 an eighth memory cell transistor being provided at one side of the seventh memory cell transistor in the third direction, 
   the control electrodes further including
 a fifth control electrode connected to a gate of the fifth memory cell transistor, 
 a sixth control electrode connected to a gate of the sixth memory cell transistor, 
 a seventh control electrode connected to a gate of the seventh memory cell transistor, and 
 an eighth control electrode connected to a gate of the eighth memory cell transistor, and 
   when a read operation to one of the fifth to eighth memory cell transistors is performed
 the first voltage is supplied to the fifth control electrode, 
 the fifth voltage is supplied to the sixth control electrode, 
 the third voltage is supplied to the seventh control electrode, and 
 the fourth voltage is supplied to the eighth control electrode.  
   
     
     
       18. The device according to claim 17, further comprising:
 a first semiconductor pillar intersecting a part of the control electrodes including the first to fourth control electrodes;   a first charge storage film provided between the part of the control electrodes and the first semiconductor pillar;   a second semiconductor pillar intersecting another part of the control electrodes including the fifth to eighth control electrodes and being connected to the first semiconductor pillar; and   a second charge storage film provided between the another part of the control electrodes and the first semiconductor pillar,   wherein   the first memory cell transistor is formed between the first control electrode and the first semiconductor pillar,   the second memory cell transistor is formed between the second control electrode and the first semiconductor pillar,   the third memory cell transistor is formed between the third control electrode and the first semiconductor pillar,   the fourth memory cell transistor is formed between the fourth control electrode and the first semiconductor pillar,   the fifth memory cell transistor is formed between the fifth control electrode and the second semiconductor pillar,   the sixth memory cell transistor is formed between the sixth control electrode and the second semiconductor pillar,   the seventh memory cell transistor is formed between the seventh control electrode and the second semiconductor pillar, and   the eighth memory cell transistor is formed between the eighth control electrode and the second semiconductor pillar.    
     
     
       19. The device according to claim 18, wherein
 the first semiconductor pillar has a first diameter at a plane in parallel with the first control electrode,   the first semiconductor pillar has a second diameter at a plane in parallel with the second control electrode, the second diameter being larger than the first diameter,   the first semiconductor pillar has a third diameter at a plane in parallel with the third control electrode, the third diameter being larger than the second diameter,   the first semiconductor pillar has a fourth diameter at a plane in parallel with the fourth control electrode, the fourth diameter being larger than the third diameter,   the second semiconductor pillar has the first diameter at a plane in parallel with the fifth control electrode,   the second semiconductor pillar has the second diameter at a plane in parallel with the sixth control electrode,   the second semiconductor pillar has the third diameter at a plane in parallel with the seventh control electrode, and   the second semiconductor pillar has the fourth diameter at a plane in parallel with the eighth control electrode.    
     
     
       20. The device according to claim 15, further comprising:
 a semiconductor pillar intersecting the control electrodes; and   a charge storage film provided between the control electrodes and the semiconductor pillar,   wherein   the first memory cell transistor is formed between the first word line and the semiconductor pillar,   the second memory cell transistor is formed between the second word line and the semiconductor pillar,   the third memory cell transistor is formed between the third word line and the semiconductor pillar, and   the fourth memory cell transistor is formed between the fourth word line and the semiconductor pillar.    
     
     
       21. The device according to claim 20, wherein
 the semiconductor pillar has a first diameter at a plane in parallel with the first control electrode,   the semiconductor pillar has a second diameter at a plane in parallel with the second control electrode, the second diameter being larger than the first diameter,   the semiconductor pillar has a third diameter at a plane in parallel with the third control electrode, the third diameter being larger than the second diameter, and   the semiconductor pillar has a fourth diameter at a plane in parallel with the fourth control electrode, the fourth diameter being larger than the third diameter.    
     
     
       22. The device according to claim 15, further comprising:
 a source line being provided at the one side of the semiconductor substrate in the third direction;   a bit line being provided at one side of the source line in the third direction,   wherein   the fourth memory cell transistor is connected to the bit line via a first selection transistor, and   the first memory cell transistor is connected to the source line via a second selection transistor.