Layout for multiple-fin SRAM cell

Abstract

The present disclosure provides a static random access memory (SRAM) cell. The SRAM cell includes a plurality of fin active regions foamed on a semiconductor substrate, wherein the plurality of fin active regions include a pair adjacent fin active regions having a first spacing and a fin active region having a second spacing from adjacent fin active regions, the second spacing being greater than the first spacing; a plurality of fin field-effect transistors (FinFETs) formed on the plurality of fin active regions, wherein the plurality of FinFETs are configured to a first and second inverters cross-coupled for data storage and at least one port for data access; a first contact disposed between the first and second the fin active regions, electrically contacting both of the first and second the fin active regions; and a second contact disposed on and electrically contacting the third fin active region.

What is claimed is: 
     
       1. A device comprising:
 a first fin active region, a second fin active region, and a third fin active region extending from a semiconductor substrate, wherein the first and second fin active regions are spaced apart from each other a first distance and the second and third fin active regions are spaced apart from each other a second distance, wherein the second distance is different than the first distance;   a plurality of fin field-effect transistors (FinFETs) formed on at least one of the first, second, and third fin active regions;   a first contact disposed on the first and second fin active regions; and   a second contact disposed on the third fin active region.   
     
     
       2. The device of  claim 1 , further comprising a fourth fin active region extending from the semiconductor substrate, the third and fourth fin active regions are spaced way from each other the second distance. 
     
     
       3. The device of  claim 1 , wherein the second distance is greater than the first distance. 
     
     
       4. The device of  claim 1 , wherein at least one of the first and second fin active regions includes an epitaxy feature formed thereon. 
     
     
       5. The device of  claim 4 , wherein the epitaxy feature includes at least one of silicon germanium and silicon carbide. 
     
     
       6. The device of  claim 1 , wherein the first contact physically contacts the first and second fin active regions. 
     
     
       7. The device of  claim 1 , wherein the plurality of FinFETs include:
 a first inverter including a first pull-up transistor (PU- 1 ) and a first and second pull-down transistors (PD- 1  and PD- 2 ); and   a second inverter including a second pull-up transistor (PU- 2 ) and a third and fourth pull-down transistors (PD- 3  and PD- 4 ), the second inverter being cross-coupled with the first inverter for data storage, and   wherein the PD- 1  and PD- 2  are formed on the first and second fin active regions, respectively.   
     
     
       8. A device comprising:
 a first fin active region, a second fin active region, and a third fin active region extending from a semiconductor substrate;   a first isolation element extending a first distance from the first fin active region to the second fin active region;   a second isolation element extending a second distance from the second fin active region to the third fin active region, wherein the second distance is different than the first distance;   a plurality of fin field-effect transistors (FinFETs) formed on at least one of the first, second, and third fin active regions;   a first contact disposed on the first and second fin active regions; and   a second contact disposed on the third fin active region.   
     
     
       9. The device of  claim 8 , wherein the first and second fin active regions have a first silicon epitaxy feature and a second silicon epitaxy feature, respectively. 
     
     
       10. The device of  claim 9 , further comprising a silicide feature formed on the first and second silicon epitaxy features. 
     
     
       11. The device of  claim 8 , further comprising a fourth fin active region extending from the semiconductor substrate; and
 a third isolation element extending the second distance from the third fin active region to the fourth fin active region.   
     
     
       12. The device of  claim 11 , wherein the second contact is not electrically coupled to the fourth fin active region. 
     
     
       13. The device of  claim 8 , wherein the plurality of FinFETs includes:
 a first pull-up device and a second pull-up device;   a first pull-down device configured with the first pull-up device to form a first inverter;   a second pull-down device configured with the second pull-up device to form a second inverter; and   a first and second pass-gate devices configured with the first and second inverters as a first port.   
     
     
       14. A method comprising:
 forming a first fin, a second fin, and a third fin extending from a substrate, wherein the first fin is spaced away from the second fin by a first distance and the second fin is spaced away from the third fin by a second distance, wherein the second distance is different than the first distance, wherein the first fin includes a first source region and a first drain region, the second fin includes a second source region and a second drain region, and the third fin includes a third source region and a third drain region;   forming a first isolation feature disposed between the first fin and the second fin and a second isolation feature disposed between the second fin and the third fin;   recessing the first fin, the second fin, and the third fin, such that a top surface of the first fin, a top surface of the second fin, and a top surface of the third fin are lower than top surfaces of the first isolation feature and the second isolation feature;   forming a gate structure wrapping the first fin, the second fin, and the third fin, such that the gate structure traverses the first source region and the first drain region of the first fin, the second source region and the second drain region of the second fin, and the third source region and the third drain region of the third fin;   forming first epitaxy features disposed on the first source region and the first drain region of the first fin, second epitaxy features disposed on the second source region and the second drain region of the second fin, and third epitaxy features disposed on the third source region and the third drain region of the third fin, wherein:
 the second epitaxy feature disposed on the second source region is merged with the first epitaxy feature disposed on the first source region, 
 the second epitaxy feature disposed on the second source region is not merged with the third epitaxy feature disposed on the third source region, and 
 the first epitaxy feature, the second epitaxy feature, and the third epitaxy feature are disposed respectively over the top surfaces of the first fin, the second fin, and the third fin, such that a portion of the second epitaxy features is disposed between the first isolation feature and the second isolation feature; 
   forming a first contact disposed on a portion of the first epitaxy feature and a portion of the second epitaxy feature disposed respectively on the first source region of the first fin and the second source region of the second fin, such that the first contact couples the first source region of the first fin and the second source region of the second fin to a first voltage line; and   forming a second contact disposed on a portion of the third epitaxy feature disposed on the third source region of the third fin, such that the second contact couples the third source region of the third fin to a second voltage line.    
     
     
       15. The method of claim 14, wherein the forming the first fin, the second fin, and the third fin and the forming the first isolation feature and the second isolation feature includes:
 etching trenches in the substrate;   filling the trenches with a dielectric material; and   etching back the dielectric material.    
     
     
       16. The method of claim 14, wherein the forming the first epitaxy features, the second epitaxy features, and the third epitaxy features is performed before a replacement process implemented for the forming the gate structure.  
     
     
       17. The method of claim 14, wherein the forming the first epitaxy features and the second epitaxy features includes growing a first semiconductor material and the forming the third epitaxy features includes growing a second semiconductor material that is different than the first semiconductor material.  
     
     
       18. The method of claim 14, further comprising forming a first metal line and a second metal line, wherein the first contact is connected to the first metal line and the second contact is connected to the second metal line, and further wherein the first metal line and the second metal line are complementary power lines.  
     
     
       19. The method of claim 14, wherein the forming the first contact and the forming the second contact includes: performing a lithography and etching process to form a first contact hole in a dielectric layer that exposes the portion of the first epitaxy feature and the portion of the second epitaxy feature and a second contact hole that exposes the portion of the third epitaxy feature; and
 depositing a conductive material in the first contact hole and the second contact hole.    
     
     
       20. The method of claim 14, further comprising configuring the first fin, the second fin, the third fin, the first epitaxy feature, the second epitaxy features, the third epitaxy features, the first contact, and the second contact to form a portion of a static random access memory (SRAM).  
     
     
       21. A method comprising:
 forming a first fin of a first fin field effect transistor (FinFET), a second fin of a second FinFET, a third fin of a third FinFET, and a fourth fin of a fourth FinFET, wherein the first, second, third, and fourth fins are oriented substantially parallel to one another, the first fin and the second fin are separated by a first distance, the third fin and the fourth fin are separated by a second distance that is greater than the first distance, the first FinFET and the second FinFET are first type FinFETs, the third FinFETs and the fourth FinFETs are second type FinFETs, and the first type is opposite the second type;   forming a single gate structure that traverses the first fin, the second fin, the third fin, and the fourth fin, such that the gate structure wraps a first portion respectively of the first fin, the second fin, the third fin, and the fourth fin;   forming a first epitaxy feature disposed on a second portion of the first fin, a second epitaxy feature disposed on a second portion of the second fin, a third epitaxy feature disposed on a second portion of the third fin, and a fourth epitaxy feature disposed on a second portion of the fourth fin, wherein the first epitaxy feature is merged with the second epitaxy feature and the third epitaxy feature is not merged with the fourth epitaxy feature;   forming a first contact disposed on the first epitaxy feature and the second epitaxy feature, wherein the first contact spans the first distance between the first fin and the second fin; and   forming a second contact disposed on the third epitaxy feature and the fourth epitaxy feature, wherein the second contact spans the second distance between the third fin and the fourth fin.    
     
     
       22. The method of claim 21, wherein:
 the forming the first epitaxy feature and the second epitaxy feature includes epitaxially growing a first semiconductor material from the second portion of the first fin and the second portion of the second fin; and   the forming the third epitaxy feature and the fourth epitaxy feature includes epitaxially growing a second semiconductor material from the second portion of the third fin and the second portion of the fourth fin, wherein the second semiconductor material is different than the first semiconductor material.    
     
     
       23. The method of claim 22, further comprising forming silicide features on the first semiconductor material and the second semiconductor material before forming the first contact and the second contact.  
     
     
       24. The method of claim 22, further comprising etching the first fin and the second fin before epitaxially growing the first semiconductor material and the third fin and the fourth fin before epitaxially growing the second semiconductor material.  
     
     
       25. The method of claim 21, wherein the second fin is separated from the third fin by the second distance.  
     
     
       26. The method of claim 21, wherein:
 the first FinFET and the second FinFET are pull-up devices;   the third FinFET and the fourth FinFET are pull-down devices; and   wherein the pull-down devices and the pull-up devices are configured to form a first inverter and a second inverter.    
     
     
       27. The method of claim 21, wherein the forming the single gate structure includes:
 forming a polysilicon gate stack over the first portion respectively of the first fin, the second fin, the third fin, and the fourth fin; and   replacing the polysilicon gate stack with a gate stack that includes a high-k gate dielectric and a metal gate electrode.    
     
     
       28. The method of claim 21, further comprising forming an interlayer dielectric layer over the first fin, the second fin, the third fin, and the fourth fin, wherein the first contact and the second contact are formed in the interlayer dielectric layer.  
     
     
       29. A method comprising:
 forming a first fin and a second fin separated by a first spacing;   forming a third fin, a fourth fin, and a fifth fin separated by a second spacing, wherein the fourth fin is disposed between the third fin and the fifth fin, and further wherein the second spacing is greater than the first spacing;   forming a first contact over the first fin and the second fin, wherein the first contact spans the first spacing, a width of the first fin, and a width of the second fin, such that the first contact extends beyond outermost sidewalls of the first fin and the second fin;   forming a second contact disposed over the third fin, the fourth fin, and the fifth fin, wherein the second contact spans the second spacing between the third fin and the fourth fin, the second spacing between the fourth fin and the fifth fin, and a width of the fourth fin, such that the second contact does not extend beyond outermost sidewalls of the third fin and the fifth fin; and   forming a single gate structure that traverses the first, second, third, fourth, and fifth fins.    
     
     
       30. The method of claim 29, further comprising:
 forming a first isolation feature separating the first fin and the second fin;   forming a second isolation feature separating the third fin and the fourth fin; and   forming a third isolation feature separating the fourth fin and the fifth fin.    
     
     
       31. The method of claim 30, further comprising:
 forming a first epitaxy feature disposed on a portion the first fin, a second epitaxy feature disposed on a portion of the second fin, a third epitaxy feature disposed on a portion of the third fin, a fourth epitaxy feature disposed on a portion of the fourth fin, and a fifth epitaxy feature disposed on a portion of the fifth fin;   wherein the first contact is disposed on the first and the second epitaxy features; and   wherein the second contact is disposed on the third, fourth, and fifth epitaxy features.    
     
     
       32. The method of claim 31, wherein:
 the forming the first epitaxy feature disposed on the portion on the first fin includes etching back the first fin, such that a top surface of the portion of the first fin is lower than a top surface of the first isolation feature;   the forming the second epitaxy feature disposed on the portion on the second fin includes etching back the second fin, such that a top surface of the portion of the second fin is lower than a top surface of the first isolation feature;   the forming the third epitaxy feature disposed on the portion on the third fin includes etching back the third fin, such that a top surface of the portion of the third fin is lower than a top surface of the second isolation feature;   the forming the fourth epitaxy feature disposed on the portion on the fourth fin includes etching back the fourth fin, such that a top surface of the portion of the fourth fin is lower than a top surface of the second isolation feature; and   the forming the fifth epitaxy feature disposed on the portion on the fifth fin includes etching back the fifth fin, such that a top surface of the portion of the fifth fin is lower than a top surface of the third isolation feature.    
     
     
       33. The method of claim 31, wherein the first epitaxy feature merges with the second epitaxy feature over the first isolation feature, the third epitaxy feature does not merge with the fourth epitaxy feature, and the fourth epitaxy feature does not merge with the fifth epitaxy feature.