Scalable polylithic on-package integratable apparatus and method

Abstract

Described is an apparatus which comprises: a first die including: a processing core; a crossbar switch coupled to the processing core; and a first edge interface coupled to the crossbar switch; and a second die including: a first edge interface positioned at a periphery of the second die and coupled to the first edge interface of the first die, wherein the first edge interface of the first die and the first edge interface of the second die are positioned across each other; a clock synchronization circuit coupled to the second edge interface; and a memory interface coupled to the clock synchronization circuit.

We claim: 
     
       1. An apparatus comprising:
 a first die including:
 a processing core; 
 a crossbar switchswitching circuitry coupled to the processing core; and 
 a first edge interface coupled to the crossbar switch switching circuitry; and 
 
 a second die including:
 a first edge interface positioned at a periphery of the second die and coupled to the first edge interface of the first die, wherein the first edge interface of the first die and the first edge interface of the second die are positioned across each other; 
 a clock synchronization circuit coupled to the second edge interface first edge interface of the second die; and 
 a memory interface coupled to the clock synchronization circuit, wherein the clock synchronization circuit includes circuitry to enable clock domain transitions across the memory interface and the first edge interface of the second die; and 
 
 a third die including:
 a first edge interface and a second edge interface, wherein the second edge interface of the third die is coupled to a second edge interface of the first die, wherein the second edge interface of the third die and the second edge interface of the first die are to be positioned across each other. 
 
 
     
     
       2. The apparatus of  claim 1 , wherein the first edge interface of the first die and the first edge interface of the second die are coupled via a package-level interconnect. 
     
     
       3. The apparatus of  claim 2 , wherein the package-level interconnect is an embedded bridge. 
     
     
       4. The apparatus of  claim 2 , wherein the package-level interconnect is a high density interposer. 
     
     
       5. The apparatus of  claim 1 , wherein the processing core of the first die is one of a compute core or an accelerator. 
     
     
       6. The apparatus of  claim 1 , wherein the second die is a memory input-output (IO) die. 
     
     
       7. The apparatus of  claim 1 , wherein each of the first edge interfaces of the first and second dies comprise an inverter. 
     
     
       8. The apparatus of  claim 1 comprises: a, wherein the third die including further includes:
 a processing core; 
 a crossbar switch switching circuitry coupled the processing core;,  
 awherein the first edge interface, coupled to the crossbar switchswitching circuitry of the third die, is to be positioned at a periphery of the third die; and a first edge interface coupled to a second edge interface of the first die, the first edge interface of the third die and the second edge interface of the first die are positioned across each other. 
 
     
     
       9. The apparatus of claim  8  1, wherein the first second edge interface of the third die and the second edge interface of the first die are coupled via a package-level interconnect. 
     
     
       10. The apparatus of  claim 8  comprises:
 a fourth die including:
 a first edge interface positioned at a periphery of the fourth die and coupled to a second third edge interface of the third die, wherein the first edge interface of the fourth die and the second third edge interface of the third die are positioned across each other; 
 
 a clock synchronization circuit coupled to the first edge interface of the fourth die; and 
 a network interface coupled to the clock synchronization circuit. 
 
     
     
       11. The apparatus of  claim 10 , wherein at least one of the first, second, third, or fourth dies is manufactured on a first process technology node, and wherein at least another one of the first, second, third, or fourth dies is manufactured on a second process technology node different from the first process technology node. 
     
     
       12. The apparatus of  claim 10 , wherein the second third edge interface of the third die and the first edge interface of the fourth die are coupled via a package-level interconnect. 
     
     
       13. The apparatus of  claim 10 , wherein the first, second, third, and fourth dies share a silicon substrate. 
     
     
       14. The apparatus of  claim 10 , wherein at least two of the first, second, third, and fourth dies have separate substrates. 
     
     
       15. The apparatus of  claim 10 , wherein the first, second, third, and fourth dies are packaged in a single package. 
     
     
       16. The apparatus of  claim 10 , wherein the fourth die is a network input-output (IO) die. 
     
     
       17. The apparatus of  claim 10 , wherein the clock synchronization circuit of the fourth die is operable to enable clock domain transitions across the network interface and the first edge interface of the fourth die. 
     
     
       18. The apparatus of claim 1, wherein the first and second dies are of different process technology nodes.  
     
     
       19. The apparatus of claim 1, wherein the first edge interface of the first die and the first edge interface of the second die are standardized edge interfaces.  
     
     
       20. The apparatus of claim 1, wherein the first die and the second die are coupled via a hierarchical fabric.  
     
     
       21. The apparatus of claim 1, further comprising memory modules coupled to the memory interface of the second die, the memory modules comprising one or more dynamic random access memories.  
     
     
       22. An apparatus comprising:
 a plurality of heterogeneous dies integrated together in a single polylithic package, the plurality of heterogeneous dies including a number of logic dies and an input-output (IO) die, the logic dies comprising:
 a respective plurality of cores, respective switching circuitry coupled to the plurality of cores, and 
 a respective communication interface coupled to the switching circuitry, and 
   the IO die comprising:
 an edge interface positioned at a periphery of the IO die; 
 a clock synchronization circuit coupled to the edge interface of the IO die; and 
 a memory interface coupled to the clock synchronization circuit; 
 wherein the clock synchronization circuit includes circuitry to enable clock domain transitions across the memory interface and the edge interface of the IO die; 
 wherein the edge interface of the IO die is coupled to the communication interface of at least one of the logic dies via a corresponding package-level interconnect; and 
 wherein at least one edge interface of the IO die and at least one edge interface of one logic die of the logic dies are coupled and positioned across each other.  
   
     
     
       23. The apparatus of claim 22, wherein the logic dies are processor dies, accelerator dies or a combination thereof.  
     
     
       24. The apparatus of claim 23, wherein the number of processor dies is 2.  
     
     
       25. The apparatus of claim 23, wherein the number of processor dies is 4.  
     
     
       26. The apparatus of claim 23, wherein the number of processor dies is 8.  
     
     
       27. The apparatus of claim 23, wherein the number of logic dies are manufactured on a first process technology node and the IO die is manufactured on a second process technology node different from the first process technology node.  
     
     
       28. The apparatus of claim 23, wherein the second die and the at least one of the logic dies are coupled via a hierarchical fabric.