Image sensor including MRAM (magnetic random access memory)

Abstract

A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) with a simplified stacked structure and improved operation characteristics includes an upper chip, in which a plurality of pixels are arranged in a two-dimensional array structure, and a lower chip below the upper chip including a logic region having logic circuits and a memory region having embedded therein magnetic random access memory (MRAM) used as image buffer memory for storing image data processed by the logic region.

What is claimed is: 
     
       1. A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) comprising:
 an upper chip, in which a plurality of pixels are arranged in a two-dimensional array structure; and 
 a lower chip, on which the upper chip is mounted, the lower chip comprising a logic region having arranged therein logic circuits and a memory region having embedded therein magnetic random access memory (MRAM), 
 wherein one or more of the logic circuits are configured to generate image data in response to signals received from the upper chip and to operate the MRAM as an image buffer memory for storing the image data generated by the logic region, 
 wherein the MRAM comprises unit cells including cell transistors and magnetic tunnel junction (MTJ) structures, the unit cells being arranged in the memory region in a two-dimensional array structure, 
 wherein the cell transistors are arranged on at a level the same as a level as at which transistors of the logic region are located, 
 wherein each MTJ structure comprises a pinned layer, a tunnel layer, and a free layer, 
 wherein each MTJ structure is positioned between two wire layers adjacent to each other from among a plurality of wire layers arranged above the cell transistors, and 
 wherein the MTJ structures are positioned between a wire layer forming a plurality of bit lines and a wire layer connected to drain regions of the cell transistors. 
 
     
     
       2. The CIS of  claim 1 , wherein the CIS is configured to operate according to a rolling shutter scheme for reading out data of the pixels row-by-row. 
     
     
       3. The CIS of  claim 1 ,
 wherein the logic region comprises an analog signal processing circuit configured to process analog pixel signals received from the pixels of the upper chip, an analog-to-digital converter (ADC) circuit configured to convert an analog signal from the analog signal processing circuit into the image data, wherein the image data is a digital signal, and an image signal processing circuit configured to process the image data, and 
 wherein the MRAM is configured to store the image data and transfer the image data to the image signal processing circuit. 
 
     
     
       4. The CIS of  claim 1 , wherein the MRAM is configured to store the image data as frame images. 
     
     
       5. The CIS of  claim 1 ,
 wherein a plurality of through substrate vias (TSVs) are formed in the upper chip, and 
 wiring of the upper chip is electrically connected to wiring of the lower chip via the TSVs. 
 
     
     
       6. The CIS of  claim 1 , wherein wiring of the upper chip is electrically connected to wiring of the lower chip via Cu—Cu direct bonding. 
     
     
       7. The CIS of  claim 1 ,
 wherein, in the upper chip, color filters and micro-lenses are formed on a backside surface of a semiconductor substrate of the upper chip, wherein wire layers are arranged on a frontside surface of the semiconductor substrate, and 
 wherein the upper chip is stacked on the lower chip such that the backside surface of the semiconductor substrate faces upward and the frontside surface of the semiconductor substrate faces toward the lower chip. 
 
     
     
       8. A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) comprising:
 an upper chip comprising a plurality of pixels arranged in a two-dimensional array structure and first wire layers arranged below the pixels, wherein each of the plurality of pixels comprises a photodiode and pixel transistors; and 
 a lower chip on which the upper chip is mounted, the lower chip comprising a logic region having logic circuits formed therein, second wire layers and a memory region having a magnetic random access memory (MRAM) cells, 
 wherein the first wire layers are electrically connected to the second wire layers, and 
 wherein the MRAM is configured to operate as an image buffer memory for storing image data processed by logic circuits of the logic region, 
 wherein the MRAM comprises unit cells including cell transistors and magnetic tunnel junction (MTJ) structures, the unit cells being arranged in the memory region in a two-dimensional array structure, 
 wherein the cell transistors are arranged on at a level the same as a level as at which transistors of the logic region are located, 
 wherein each MTJ structure comprises a pinned layer, a tunnel layer, and a free layer, 
 wherein each MTJ structure is positioned between two wire layers adjacent to each other from among a plurality of wire layers arranged above the cell transistors, and 
 wherein the MTJ structures are positioned between a wire layer forming a plurality of bit lines and a wire layer connected to drain regions of the cell transistors. 
 
     
     
       9. The CIS of  claim 8 ,
 wherein through substrate vias (TSVs) are formed in at a portion of the upper chip that does not include the pixels, and 
 wherein the first wire layers are electrically connected to the second wire layers via the TSVs. 
 
     
     
       10. The CIS of  claim 8 , wherein the first wire layers are electrically connected to the second wire layers via Cu—Cu direct bonding. 
     
     
       11. The CIS of  claim 8 ,
 wherein the CIS is configured to operate according to a rolling shutter scheme for reading out data of the pixels row-by-row, 
 wherein the logic circuits constitute an analog signal processing circuit configured to process analog pixel signals received from pixels of the upper chip, an analog-to-digital converter (ADC) circuit configured to convert an analog signal from the analog signal processing circuit into the image data, wherein the image data is a digital signal, and an image signal processing circuit configured to process the image data, and 
 wherein the MRAM is configured to store the image data and transfer the image data to the image signal processing circuit. 
 
     
     
       12. A CMOS image sensor comprising:
 a lower semiconductor chip; and 
 an upper semiconductor chip mounted on the upper lower semiconductor chip, 
 wherein the upper semiconductor chip comprises
 an array of pixels, each pixel comprising a photodiode positioned to receive light from a light source external to the CMOS image sensor and connected to a source follower transistor, the source follower transistor configured to provide an analog pixel signal corresponding to a charge accumulated by the corresponding photodiode, 
 a plurality of column signal lines, each column signal line connected to a column of pixels to receive corresponding analog pixel signals, and 
 a plurality of row lines, each row line connected to a corresponding row of pixels to connect each of the pixels of the row of pixels to a corresponding source follower transistor to provide the corresponding analog pixel signal to the corresponding column signal line, 
 
 wherein the lower semiconductor chip comprises
 a logic region having arranged therein logic circuits including an analog to digital converter configured to provide digital pixel data correlated to analog pixel signals provided by the plurality of column signal lines, and 
 a memory region, having embedded therein a magnetic random access memory (MRAM) configured to receive and store image frame data resulting from the digital pixel data provide by the analog to digital converter, 
 
 wherein the MRAM comprises unit cells including cell transistors and magnetic tunnel junction (MTJ) structures, the unit cells being arranged in the memory region in a two-dimensional array structure, 
 wherein the cell transistors are arranged on at a level the same as a level as at which transistors of the logic region are located, 
 wherein each MTJ structure comprises a pinned layer, a tunnel layer, and a free layer, 
 wherein each MTJ structure is positioned between two wire layers adjacent to each other from among a plurality of wire layers arranged above the cell transistors, and 
 wherein the MTJ structures are positioned between a wire layer forming a plurality of bit lines and a wire layer connected to drain regions of the cell transistors. 
 
     
     
       13. The CMOS image sensor of  claim 12 , wherein the lower semiconductor chip further comprises a plurality of first circuits each directly connected to a corresponding column signal line. 
     
     
       14. The CMOS image sensor of  claim 13 , wherein each of the plurality of first circuits of the lower semiconductor chip comprise a correlated-double sampling circuit directly connected to a column signal line of the upper semiconductor chip and having an output connected to the analog to digital converter of the lower semiconductor chip. 
     
     
       15. The CMOS image sensor of  claim 12 , wherein the lower semiconductor chip further comprises a row driver drive circuit directly connected to the row lines of the upper semiconductor chip to activate selected ones of the row lines. 
     
     
       16. The CMOS image sensor of  claim 12 ,
 wherein the lower semiconductor chip comprises a semi-conductor substrate, and 
 wherein transistors of the MRAM and transistors of the analog to digital converter each comprise source/drain regions formed within the semiconductor substrate. 
 
     
     
       17. An image sensor comprising:
 a first part including a plurality of pixels, each of the plurality of pixels including a photodiode; and   a second part configured to be electrically connected to the first part, and including a plurality of magnetic random access memory (MRAM) cells arranged in a two-dimensional array,   wherein the first part is stacked on the second part,   at least two pixels among the plurality of pixels share a plurality of transistors and a floating diffusion region, and   the second part comprises:   a substrate including a first surface that has a first region and a second region;   a first gate and a first source/drain disposed on the first region of the first surface of the substrate and forming a first transistor;   a second gate and a second source/drain disposed on the second region of the first surface of the substrate and forming a second transistor that is at a level the same as a level at which the first transistor is located;   a first contact disposed on the first source/drain and disposed on the first region of the first surface of the substrate;   a first wire layer disposed on the first contact;   a second contact disposed on the first wire layer;   a second wire layer disposed on the second contact, a width of the second wire layer being greater than a width of the first wire layer;   a third contact disposed on the second source/drain and disposed on the second region of the first surface of the substrate;   a third wire layer disposed on the third contact;   a magnetic tunnel junction (MTJ) structure disposed on the third wire layer, and including a pinned layer, a tunnel layer and a free layer; and   a fourth wire layer disposed on the MTJ structure and forming a plurality of bit lines, the third wire layer and the fourth wire layer being adjacent to each other among wire layers on the second source/drain.    
     
     
       18. The image sensor of claim 17, wherein a width of a lower portion of the first contact is less than a width of an upper portion of the first contact, and
 a width of a lower portion of the third contact is less than a width of an upper portion of the third contact.    
     
     
       19. The image sensor of claim 17, wherein the first region of the first surface of the substrate is a logic region, and the second region of the first surface of the substrate is a memory region.  
     
     
       20. The image sensor of claim 17, wherein four pixels among the plurality of pixels share the plurality of transistors and the floating diffusion region.  
     
     
       21. The image sensor of claim 17, wherein the plurality of transistors include:
 a reset transistor configured to reset floating charge;   a source follower transistor configured to provide an analog pixel signal to a column signal line; and   a select transistor configured to connect the analog pixel signal to the column signal line.    
     
     
       22. The image sensor of claim 17, wherein the first wire layer is on the same level as the third wire layer, and
 the second wire layer is at the same vertical level as the fourth wire layer.    
     
     
       23. The image sensor of claim 17, wherein the second part further comprises:
 a fifth contact disposed on the second wire layer;   a fifth wire layer disposed on the fifth contact;   a fourth contact disposed on the fourth wire layer; and   a sixth wire layer disposed on the fourth contact.    
     
     
       24. The image sensor of claim 17, wherein the MTJ structure is at least partially overlapped with the third contact.  
     
     
       25. The image sensor of claim 17, wherein the pinned layer includes PtMn, IrMn, MnO, MnS, MnTe, MnF2, FeCl2, FeO, CoCl2, CoO, NiCl2, NiO or Cr,
 the tunnel layer includes magnesium (Mg), titanium (Ti), aluminum (Al), magnesium-zinc (MgZn), magnesium-boron (MgB), titanium (Ti) or vanadium (V), and   the free layer includes cobalt (Co), iron (Fe), nickel (Ni), FeB, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO or Y3Fe5O12.    
     
     
       26. The image sensor of claim 17, wherein the first part and the second part are connected to each other via a through substrate via (TSV).  
     
     
       27. The image sensor of claim 17, wherein the first part and the second part are bonded to each other using Cu—Cu direct bonding.  
     
     
       28. The image sensor of claim 17, wherein color filters and micro-lenses are disposed on a first surface of a substrate of the first part,
 wire layers of the first part are arranged on a second surface of the substrate of the first part, and   the second surface of the substrate of the first part faces toward the second part.    
     
     
       29. The image sensor of claim 17, wherein the image sensor is configured to operate according to a rolling shutter scheme for reading out data of the plurality of pixels row-by-row.  
     
     
       30. The image sensor of claim 17, wherein the second part includes:
 a row drive circuit configured to drive pixels among the plurality of pixels;   a column signal processing circuit configured to perform a signal processing with respect to signals output from the plurality of pixels;   an image buffer memory configured to store image data processed by the column signal processing circuit, and including the plurality of magnetic random access memory (MRAM) cells arranged in the two-dimensional array;   an output circuit configured to output the image data transferred from the image buffer memory; and   a control circuit configured to control overall operations of the row drive circuit, the column signal processing circuit, the image buffer memory and the output circuit by generating one or more clock signals and/or one or more control signals.    
     
     
       31. An image sensor comprising:
 a first chip including a plurality of pixels, each of the plurality of pixels including a photodiode; and   a second chip electrically connected to the first chip, and including a plurality of magnetic random access memory (MRAM) cells arranged in a two-dimensional array,   wherein the second chip comprises:   a substrate including a first surface that has a first region and a second region;   a first gate and a first source/drain disposed on the first region of the first surface of the substrate and forming a first transistor;   a second gate and a second source/drain disposed on the second region of the first surface of the substrate and forming a second transistor that is at a level the same as a level at which the first transistor is located;   a first contact disposed on the first source/drain and disposed on the first region of the first surface of the substrate;   a first wire layer disposed on the first contact;   a second contact disposed on the first wire layer;   a second wire layer disposed on the second contact;   a third contact disposed on the second wire layer;   a third wire layer disposed on the third contact, a width of the third wire layer being greater than the width of the first wire layer;   a fourth contact disposed on the second source/drain and disposed on the second region of the first surface of the substrate;   a fourth wire layer disposed on the fourth contact;   a fifth contact disposed on the fourth wire layer;   a fifth wire layer disposed on the fifth contact;   a magnetic tunnel junction (MTJ) structure disposed on the fifth wire layer, and including a pinned layer, a tunnel layer and a free layer; and   a sixth wire layer disposed on the MTJ structure and forming a plurality of bit lines, the fifth wire layer and the sixth wire layer being adjacent to each other among wire layers on the second source/drain,   wherein the first chip is stacked on the second chip.    
     
     
       32. The image sensor of claim 31, wherein two pixels among the plurality of pixels share a plurality of transistors and a floating diffusion region.  
     
     
       33. The image sensor of claim 31, wherein four pixels among the plurality of pixels share a plurality of transistors and a floating diffusion region.  
     
     
       34. The image sensor of claim 31, wherein a width of a lower portion of the first contact is less than a width of an upper portion of the first contact, and
 a width of a lower portion of the fourth contact is less than a width of an upper portion of the fourth contact.    
     
     
       35. The image sensor of claim 31, wherein the first region of the first surface of the substrate is a logic region, and the second region of the first surface of the substrate is a memory region.  
     
     
       36. The image sensor of claim 31, wherein the second chip includes:
 a row drive circuit configured to drive pixels among the plurality of pixels;   a column signal processing circuit configured to perform a signal processing with respect to signals output from the plurality of pixels;   an image buffer memory configured to store image data processed by the column signal processing circuit, and including the plurality of magnetic random access memory (MRAM) cells arranged in the two-dimensional array;   an output circuit configured to output the image data transferred from the image buffer memory;   a control circuit configured to control overall operations of the row drive circuit, the column signal processing circuit, the image buffer memory and the output circuit by generating one or more clock signals and/or one or more control signals.    
     
     
       37. An image sensor comprising:
 a first chip including a plurality of pixels, each of the plurality of pixels including a photodiode; and   a second chip electrically connected to the first chip, and including a row drive circuit, a column signal processing circuit, an image buffer memory, an output circuit and a control circuit,   wherein the row drive circuit is configured to drive pixels among the plurality of pixels,   the column signal processing circuit is configured to perform a signal processing with respect to signals output from the plurality of pixels,   the image buffer memory is configured to store image data processed by the column signal processing circuit, and including a plurality of magnetic random access memory (MRAM) cells arranged in a two-dimensional array,   the output circuit is configured to output the image data transferred from the image buffer memory,   the control circuit is configured to control overall operations of the row drive circuit, the column signal processing circuit, the image buffer memory and the output circuit by generating one or more clock signals and/or one or more control signals, and   the second chip comprises:   a substrate including a first surface that has a first region and a second region;   a first gate and a first source/drain disposed on the first region of the first surface of the substrate and forming a first transistor;   a second gate and a second source/drain disposed on the second region of the first surface of the substrate and forming a second transistor that is at a level the same as a level at which the first transistor is located;   a first contact disposed on the first source/drain and disposed on the first region of the first surface of the substrate;   a first wire layer disposed on the first contact;   a second contact disposed on the first wire layer;   a second wire layer disposed on the second contact;   a third contact disposed on the second wire layer;   a third wire layer disposed on the third contact;   a fourth contact disposed on the second source/drain and disposed on the second region of the first surface of the substrate;   a fourth wire layer disposed on the fourth contact;   a fifth contact disposed on the fourth wire layer;   a fifth wire layer disposed on the fifth contact;   a magnetic tunnel junction (MTJ) structure disposed on the fifth wire layer, and including a pinned layer, a tunnel layer and a free layer, the MTJ structure directly contacting the fifth wire layer; and   a sixth wire layer disposed on the MTJ structure and forming a plurality of bit lines, the sixth wire layer directly contacting the MTJ structure,   wherein the first chip is stacked on the second chip.    
     
     
       38. The image sensor of claim 37, wherein a width of the second wire layer is greater than a width of the first wire layer,
 a width of the third wire layer is greater than the width of the second wire layer,   a width of the fifth wire layer is greater than a width of the fourth wire layer, and   a width of the sixth wire layer is greater than the width of the fifth wire layer.    
     
     
       39. The image sensor of claim 37, wherein at least two pixels among the plurality of pixels share a plurality of transistors and a floating diffusion region.  
     
     
       40. The image sensor of claim 37, wherein four pixels among the plurality of pixels share a plurality of transistors and a floating diffusion region.