Semiconductor device having gate electrode with spacers on fin structure and silicide layer filling the recess

Abstract

An semiconductor device is provided. A fin is disposed on a substrate, extending in a lengthwise direction. A first recess is disposed on a sidewall of the fin so that the fin and the first recess is arranged in a straight line along the lengthwise direction. A gate structure crosses the fin in the first direction crossing the lengthwise direction. A spacer is disposed on sidewalk of the gate structure. A source/drain region is disposed in the first recess. The source/drain region is formed under the spacer. A silicide layer is disposed on the source/drain region. The silicide layer and the source/drain region fill the first recess.

What is claimed is: 
     
       1. A semiconductor device comprising:
 a substrate; 
 a fin disposed on the substrate to extend in a first direction; 
 a trench disposed on the fin and including a bottom surface and opposing sidewalls formed by the fin, wherein the trench is arranged in a straight line along a second direction crossing the first direction; 
 a gate structure crossing the fin in the first second direction; 
 a spacer disposed on sidewalls of the gate structure; 
 a source/drain region solely disposed in empty space of the trench positioned between the opposing sidewalls of the trench, on at least one side of the gate structure to be disposed in the fin and, the source/drain region including a first recess, a bottom surface of the first recess is nearer to a top surface of the substrate than a top surface of the fin; and 
 a silicide layer filling the first recess. 
 
     
     
       2. The semiconductor device of  claim 1 , wherein the source/drain region is U-shaped in view of a cross section taken in the lengthwise first direction. 
     
     
       3. The semiconductor device of  claim 1 , wherein the source/drain region is in contact with the substrate. 
     
     
       4. The semiconductor device of  claim 1 , wherein a bottom surface of the silicide layer is lower than a top surface of the fin. 
     
     
       5. The semiconductor device of  claim 1 , wherein the spacer includes a first spacer and a second spacer, the first spacer is interposed between the gate structure and the second spacer, and a top surface of the source/drain region is in contact with the second spacer. 
     
     
       6. The semiconductor device of  claim 5 , wherein a distance between the source/drain region and the gate structure is greater than or equal to a width of a bottom surface of the first spacer. 
     
     
       7. The semiconductor device of  claim 5 , wherein an outer surface of the second spacer is connected to a surface of the first recess without forming a step at a boundary between the second spacer and the first recess. 
     
     
       8. The semiconductor device of  claim 1 , wherein the source/drain region includes a first source/drain region and a second source/drain region, wherein the first source/drain region is interposed between the trench and the second source/drain region. 
     
     
       9. The semiconductor device of  claim 8 , wherein a sum of a width of a top surface of the first source/drain region and a width of a top surface of the second source/drain region is smaller than or equal to a width of a bottom surface of the spacer. 
     
     
       10. The semiconductor device of  claim 9 , wherein the first source/drain region and the second source/drain region are doped with a first impurity, and a concentration of the first impurity in the first source/drain region is different from that of the first impurity in the second source/drain region. 
     
     
       11. A semiconductor device comprising:
 a substrate; 
 a fin formed on the substrate, wherein the fin includes a first fin protrusion and a second fin protrusion formed on the substrate; 
 a first recess disposed between the first fin protrusion and the second fin protrusion and including a bottom surface and opposing sidewalls formed by the fin, wherein the first recess, the first fin protrusion and the second fin protrusion are arranged in a straight line along a first direction; 
 a first gate structure and a second gate structure crossing the first fin protrusion and the second fin protrusion in a second direction, respectively; 
 a first spacer and a second spacer disposed on inner sidewalls of the first gate structure and the second gate structure, respectively, wherein the inner sidewalls face each other through the first recess; 
 a source/drain region solely disposed in empty space of the first recess positioned between the opposing sidewalls of the first recess, wherein one end of the source/drain region is disposed under the first spacer and another end of the source drain/region is disposed under the second spacer, and 
 a silicide layer disposed on the source/drain region, wherein the silicide layer and the source/drain region fill the first recess. 
 
     
     
       12. The semiconductor device of  claim 11 , wherein the source/drain region is U-shaped in view of a cross section taken in the first direction. 
     
     
       13. The semiconductor device of  claim 12 , wherein the source/drain region is in contact with the substrate. 
     
     
       14. The semiconductor device of  claim 11 , wherein the source/drain region includes a first source/drain region and a second source/drain region, and wherein the first source/drain region is interposed between the substrate and the second source/drain region. 
     
     
       15. The semiconductor device of  claim 11 , further comprising a contact disposed on the silicide layer. 
     
     
       16. A semiconductor device comprising:
 a substrate;   a fin disposed on the substrate to extend in a first direction;   a trench disposed on the fin and including a bottom surface and opposing sidewalls formed by the fin, wherein the trench is arranged in a straight line along a second direction crossing the first direction;   a plurality of channel patterns spaced apart from the substrate, each of the plurality of channel patterns being spaced apart from each other, the plurality of channel patterns defines at least a portion of the opposing sidewalls of the trench;   a gate structure crossing the fin in the second direction and surrounding each of the plurality of channel patterns;   a spacer disposed on sidewalls of the gate structure;   a source/drain region including metal, the source/drain region is solely disposed in empty space of the trench positioned between the opposing sidewalls of the trench on at least one side of the gate structure to be disposed in the fin and includes a first recess, a bottom surface of the first recess is nearer to a top surface of the substrate than a top surface of the fin; and   the metal includes a silicide layer filling the first recess.   
     
     
       17. The semiconductor device of claim 16, wherein the metal includes at least one of Pt, Ni and Co. 
     
     
       18. The semiconductor device of claim 16, wherein the plurality of channel patterns includes a first channel pattern and a second channel pattern, the first channel pattern is spaced apart from the second channel pattern in the thickness direction of the substrate. 
     
     
       19. The semiconductor device of claim 16, wherein he metal is in contact with the plurality of channel patterns. 
     
     
       20. The semiconductor device of claim 16, wherein the gate structure surrounds a periphery of each of channel patterns.