Memory interface with selectable connections for input receiver circuits based on operating mode

Abstract

A method of operating an input/output interface includes selecting one of a plurality of output driver circuits according to a mode selection signal, and outputting a data signal using the selected one of the plurality of output driver circuits. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an on-die termination (ODT) circuit included in the input/output interface according to the mode selection signal. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an ODT circuit included in the input/output interface according to the mode selection signal.

What is claimed is: 
     
       1. An input/output interface for a memory device comprising:
 a mode selection circuit configured to generate a mode selection signal; and   an output driver block configured to be connected to an input/output pad and to transmit an output data signal, the input/output pad being terminated with one of a VSSQ termination, a VDDQ termination and a termination off mode based on the mode selection signal, and the output driver block comprising a plurality of output driver circuits, and one of the plurality of output driver circuits being configured to selectively operate during transmitting the output data signal based on the mode selection signal,   wherein each of the plurality of output driver circuits has different topology suitable for different operation speed, the operation speed selected from a group including a low speed operation, and a high speed operation faster than the low speed operation.   
     
     
       2. The input/output interface of  claim 1 , wherein the VSSQ termination has a termination level of a ground voltage level and the VDDQ termination has a termination level of a supply voltage level respectively. 
     
     
       3. The input/output interface of  claim 1 , wherein the mode selection signal is configured to receive operating frequency information for selecting one among a plurality of on-die termination (ODT) circuits. 
     
     
       4. The input/output interface of  claim 3 , wherein the mode selection signal is configured to select the termination off mode if the operating frequency information indicates the low speed operation. 
     
     
       5. The input/output interface of  claim 3 , wherein the mode selection signal is configured to select the VDDQ termination if the operating frequency information indicates an intermediate speed operation which is faster than the low speed operation but slower than the high speed operation. 
     
     
       6. The input/output interface of  claim 3 , wherein the mode selection signal is configured to select the VSSQ termination if the operating frequency information indicates the high speed operation. 
     
     
       7. The input/output interface of  claim 3 , wherein the mode selection signal is configured to select a first output driver circuit among the plurality of the output driver circuits if the operating frequency information indicates the high speed operation, wherein pull-up driver of the first output driver circuit comprises a NMOS transistor. 
     
     
       8. The input/output interface of  claim 3 , wherein the mode selection signal is configured to select a second output driver circuit among the plurality of the output driver circuits if the operating frequency information indicates one of an intermediate speed operation and the low speed operation, the intermediate speed operation being faster than the low speed operation and slower than the high speed operation, wherein pull-up driver of the second output driver circuit comprises a PMOS transistor. 
     
     
       9. An input/output interface for a memory device comprising:
 a mode selection circuit configured to generate a mode selection signal;   a termination circuit configured to provide the input/output interface with one of a VSSQ termination, a VDDQ termination and a termination off mode in response to the mode selection signal; and   an output driver block configured to transmit a data output signal, the output driver block being connected to an input/output pad and comprising a plurality of output driver circuits, wherein one of the plurality of output driver circuits is configured to selectively operate according to the mode selection signal, the mode selection signal indicating a termination type of the termination circuit,   wherein each of the plurality of output driver circuits has different topology suitable for different operation speed, the operation speed selected from a group including a low speed operation, and a high speed operation faster than the low speed operation.   
     
     
       10. The input/output interface of  claim 9 , wherein the VSSQ termination has a termination level of a ground voltage level and the VDDQ termination has a termination level of a supply voltage level respectively. 
     
     
       11. The input/output interface of  claim 9 , wherein the mode selection signal is configured to receive operating frequency information for selecting one among a plurality of on-die termination (ODT) circuits. 
     
     
       12. The input/output interface of  claim 11 , wherein the mode selection signal is configured to select the termination off mode if the operating frequency information indicates the low speed operation. 
     
     
       13. The input/output interface of  claim 11 , wherein the mode selection signal is configured to select the VDDQ termination if the operating frequency information indicates an intermediate speed operation, the intermediate speed operation faster than the low speed operation and slower than the high speed operation. 
     
     
       14. The input/output interface of  claim 11 , wherein the mode selection signal is configured to select the VSSQ termination if the operating frequency information indicates the high speed operation. 
     
     
       15. The input/output interface of  claim 11 , wherein the mode selection signal is configured to select a first output driver circuit among the plurality of the output driver circuits if the operating frequency information indicates the high speed operation, wherein pull-up driver of the first output driver circuit comprises a NMOS transistor. 
     
     
       16. The input/output interface of  claim 11 , wherein the mode selection signal is configured to select a second output driver circuit among the plurality of the output driver circuits if the operating frequency information indicates one of an intermediate speed operation faster than the low speed operation and slower than the high speed operation, and the low speed operation, wherein pull-up driver of the second output driver circuit comprises a PMOS transistor. 
     
     
       17. An input/output interface circuit for a memory device comprising:
 a mode selection circuit configured to generate a mode selection signal;   a termination circuit configured to provide the input/output interface with one of a VSSQ termination, a VDDQ termination and a termination off mode in response to the mode selection signal; and   an output driver block connected to an input/output pad including,
 a first output driver circuit configured to transmit a output data signal, the first output driver circuit including a NMOS pull-up driver; and 
 a second output driver circuit configured to transmit the output data signal, the second output driver circuit including a PMOS pull-up driver, 
   wherein one of the first output driver circuit and the second output driver circuit is selected to transmit the output data signal in response to the mode selection signal.   
     
     
       18. The input/output interface of  claim 17 , wherein the VSSQ termination has a termination level of a ground voltage level and the VDDQ termination has a termination level of a supply voltage level respectively. 
     
     
       19. The input/output interface of  claim 17 , wherein the mode selection circuit is configured to receive operating frequency information for selecting one among a plurality of on-die termination (ODT) circuits. 
     
     
       20. The input/output interface of  claim 19 , wherein the mode selection signal is configured to select the first output driver circuit if the operating frequency information indicates a high speed operation. 
     
     
       21. The input/output interface of  claim 19 , wherein the mode selection signal is configured to select the second output driver circuit if the operating frequency information indicates one of a medium speed operation and a low speed operation. 
     
     
       22. An input/output interface circuit for a memory controller, the input/output interface circuit comprising:
 a mode register configured to store an operation mode of the memory controller, the operation mode indicating one of a first operation mode and a second operation mode;   an input receiver block connected with an input/output pad, the input receiver block including a first input receiver circuit and a second input receiver circuit, and one of the first input receiver circuit and the second input receiver circuit being selectively connected to the input/output pad according to the operation mode and receiving an input data signal;   a first on-die-termination (ODT) circuit connected between the input/output pad and a supply node at a supply voltage level VDDQ, and selectively turned on or turned off according to the operation mode; and   a second on-die-termination (ODT) circuit connected between the input/output pad and a ground node at a ground voltage level VSSQ, and selectively turned on or turned off according to the operation mode,   wherein, when the operation mode indicates the first operation mode, the first input receiver circuit is connected to the input/output pad and receives the input data signal while the first ODT circuit is turned on, and when the operation mode indicates the second operation mode, the second input receiver circuit is connected to the input/output pad and receives the input data signal while the second ODT circuit is turned on.   
     
     
       23. The input/output interface circuit of claim 22, wherein the first input receiver circuit comprises a N-type differential amplifier in which the input data signal is inputted to a gate node of a NMOS transistor of the N-type differential amplifier. 
     
     
       24. The input/output interface circuit of claim 22, wherein the second input receiver circuit comprises a P-type differential amplifier in which the input data signal is inputted to a gate node of a PMOS transistor of the P-type differential amplifier. 
     
     
       25. The input/output interface circuit of claim 22, wherein, when the operation mode indicates the first operation mode, the input data signal swings near the supply voltage level VDDQ, and when the operation mode indicates the second operation mode, the input data signal swings near the ground voltage level VSSQ. 
     
     
       26. The input/output interface circuit of claim 22, wherein the second ODT circuit is turned off while the first ODT circuit is turned on, the first ODT circuit is turned off while the second ODT circuit is turned on. 
     
     
       27. The input/output interface circuit of claim 22, wherein the input/output interface further includes an output driver block connected with the input/output pad, the output driver block includes a first output driver circuit and a second output driver circuit, and one of the first output driver circuit and the second output driver circuit is selectively connected to the input/output pad according to the operation mode and drives an output data signal while the first and second ODT circuits are turned-off. 
     
     
       28. The input/output interface circuit of claim 27, wherein the first output driver circuit includes a pull-down NMOS device and the second output driver circuit includes a pull-up NMOS device respectively. 
     
     
       29. The input/output interface circuit of claim 27, wherein the first output driver circuit includes a pull-down NMOS device and the second output driver circuit includes a pull-up PMOS device respectively. 
     
     
       30. The input/output interface circuit of claim 22, wherein the first ODT circuit comprises a first ODT switch and a first termination resistor connected in series, and one end of the first ODT circuit is connected to the input/output pad and the other end of the first ODT circuit is connected to the supply node at the supply voltage level VDDQ, and the second ODT circuit comprises a second ODT switch and a second termination resistor connected in series, and one end of the second ODT circuit is connected to the input/output pad and the other end of the second ODT circuit is connected to the ground node at the ground voltage level VSSQ. 
     
     
       31. The input/output interface circuit of claim 30, wherein the first ODT circuit is turned on by connecting the first ODT switch and is turned off by disconnecting the first ODT switch, and the second ODT circuit is turned on by connecting the second ODT switch and is turned off by disconnecting the second ODT switch. 
     
     
       32. A memory system comprising:
 a memory controller including a first internal circuit and a first input/output (I/O) interface, wherein the first I/O interface includes:   a mode register configured to store an operation mode of the memory controller, the operation mode indicating one of a first operation mode and a second operation mode;   a first input receiver block connected with a first input/output pad, the first input receiver block including a first input receiver circuit and a second input receiver circuit, and one of the first input receiver circuit and the second input receiver circuit being selectively connected to the first input/output pad according to the operation mode and receiving an input data signal;   a first output driver block connected with the first input/output pad, the first output driver block including a first output driver circuit and a second output driver circuit, and one of the first output driver circuit and the second output driver circuit being selectively connected to the first input/output pad according to the operation mode and driving an output data signal;   a first on-die-termination (ODT) circuit connected between the first input/output pad and a supply node at a supply voltage level VDDQ, and selectively turned on or turned off according to the operation mode; and   a second on-die-termination (ODT) circuit connected between the first input/output pad and a ground node at a ground voltage level VSSQ, and selectively turned on or turned off according to the operation mode; and   a memory device connected to the memory controller through a data but, the memory device including a second internal circuit and a second input/output (I/O) interface, wherein the second I/O interface includes:   a second input receiver block connected with a second input/output pad, the second input receiver block including one of third input receiver circuit and fourth input receiver circuit according to the operation mode, and receiving the output data signal;   a second output driver block connected with the second input/output pad, the second output driver block including one of third output driver circuit and fourth output driver circuit according to the operation mode, and outputting the input data signal;   a termination circuit including one of a third on-die-termination (ODT) circuit connected between the second input/output pad and the supply node at the supply voltage level VDDQ and a fourth on-die-termination (ODT) circuit connected between the second input/output pad and the ground node at the voltage level VSSQ according to the operation mode,   wherein, when the operation mode indicates the first operation mode, the first input receiver circuit is connected to the input/output pad and receives the input data signal while the first ODT circuit is turned on, and when the operation mode indicates the second operation mode, the second input receiver circuit is connected to the input/output pad and receives the input data signal while the second ODT circuit is turned on.   
     
     
       33. The memory system of claim 32, wherein, when the operation mode indicates the first operation mode, the second output driver block includes the third output driver circuit and the third output driver circuit drives the input data signal to the first input/output pad through the data bus while the first ODT circuit is turned on and the second ODT circuit is turned off, and when the operation mode indicates the second operation mode, the second output driver block includes the fourth output driver circuit and the fourth output driver circuit drives the input data signal to the first input/output pad while the first ODT circuit is turned off and the second ODT circuit is turned on. 
     
     
       34. The input/output interface circuit of claim 32, wherein the first output driver circuit includes a pull-down NMOS device and the second output driver circuit includes a pull-up NMOS device respectively. 
     
     
       35. The input/output interface circuit of claim 32, wherein the first output driver circuit includes a pull-down NMOS device and the second output driver circuit includes a pull-up PMOS device respectively. 
     
     
       36. The input/output interface circuit of claim 32, wherein the first ODT circuit comprises a first ODT switch and a first termination resistor connected in series, and one end of the first ODT circuit is connected to the input/output pad and the other end of the first ODT circuit is connected to the supply node at the supply voltage level VDDQ, and the second ODT circuit comprises a second ODT switch and a second termination resistor connected in series, and one end of the second ODT circuit is connected to the input/output pad and the other end of the second ODT circuit is connected to the ground node at the ground voltage level VSSQ. 
     
     
       37. The input/output interface circuit of claim 36, wherein the first ODT circuit is turned on by connecting the first ODT switch and is turned off by disconnecting the first ODT switch, and the second ODT circuit is turned on by connecting the second ODT switch and is turned off by disconnecting the second ODT switch. 
     
     
       38. The input/output interface circuit of claim 32, wherein the first input receiver circuit comprises a N-type differential amplifier in which the input data signal is inputted to a gate node of a NMOS transistor of the N-type differential amplifier. 
     
     
       39. The input/output interface circuit of claim 32, wherein the second input receiver circuit comprises a P-type differential amplifier in which the input data signal is inputted to a gate node of a PMOS transistor of the P-type differential amplifier. 
     
     
       40. The input/output interface circuit of claim 32, wherein, when the operation mode indicates the first operation mode, the input data signal swings near the supply voltage level VDDQ, and when the operation mode indicates the second operation mode, the input data signal swings near the ground voltage level VSSQ. 
     
     
       41. An input/output interface circuit for a memory controller, the input/output interface circuit comprising:
 a mode register configured to store an operation mode of the memory controller, the operation mode indicating one of a first operation mode and a second operation mode;   an input receiver block connected with an input/output pad, and receiving an input data signal;   a first on-die-termination (ODT) circuit connected between the input/output pad and a supply node at a supply voltage level VDDQ, and selectively turned on or turned off according to the operation mode; and   a second on-die-termination (ODT) circuit connected between the input/output pad and a ground node at a ground voltage level VSSQ, and selectively turned on or turned off according to the operation mode,   wherein, when the operation mode indicates the first operation mode, the input receiver block receives the input data signal while the first ODT circuit is turned on, and when the operation mode indicates the second operation mode, the input receiver block receives the input data signal while the second ODT circuit is turned on.   
     
     
       42. The input/output interface circuit of claim 41, wherein the input receiver block includes a first input receiver circuit and a second input receiver circuit, and one of the first input receiver circuit and the second input receiver circuit is selectively connected to the input/output pad according to the operation mode. 
     
     
       43. The input/output interface circuit of claim 42, wherein the first input receiver circuit comprises a N-type differential amplifier in which the input data signal is inputted to a gate node of a NMOS transistor of the N-type differential amplifier. 
     
     
       44. The input/output interface circuit of claim 42, wherein the second input receiver circuit comprises a P-type differential amplifier in which the input data signal is inputted to a gate node of a PMOS transistor of the P-type differential amplifier. 
     
     
       45. The input/output interface circuit of claim 41, wherein, when the operation mode indicates the first operation mode, the input data signal swings near the supply voltage level VDDQ, and when the operation mode indicates the second operation mode, the input data signal swings near the ground voltage level VSSQ. 
     
     
       46. The input/output interface circuit of claim 41, wherein the second ODT circuit is turned off while the first ODT circuit is turned on, the first ODT circuit is turned off while the second ODT circuit is turned on. 
     
     
       47. The input/output interface circuit of claim 41, wherein the input/output interface further includes an output driver block connected with the input/output pad, the output driver block includes a first output driver circuit and a second output driver circuit, and one of the first output driver circuit and the second output driver circuit is selectively connected to the input/output pad according to the operation mode and drives an output data signal while the first and second ODT circuits are turned-off. 
     
     
       48. The input/output interface circuit of claim 47, wherein the first output driver circuit includes a pull-down NMOS device and the second output driver circuit includes a pull-up NMOS device respectively. 
     
     
       49. The input/output interface circuit of claim 47, wherein the first output driver circuit includes a pull-down NMOS device and the second output driver circuit includes a pull-up PMOS device respectively. 
     
     
       50. The input/output interface circuit of claim 41, wherein the first ODT circuit comprises a first ODT switch and a first termination resistor connected in series, and one end of the first ODT circuit is connected to the input/output pad and the other end of the first ODT circuit is connected to the supply node at the supply voltage level VDDQ, and the second ODT circuit comprises a second ODT switch and a second termination resistor connected in series, and one end of the second ODT circuit is connected to the input/output pad and the other end of the second ODT circuit is connected to the ground node at the ground voltage level VSSQ. 
     
     
       51. The input/output interface circuit of claim 50, wherein the first ODT circuit is turned on by connecting the first ODT switch and is turned off by disconnecting the first ODT switch, and the second ODT circuit is turned on by connecting the second ODT switch and is turned off by disconnecting the second ODT switch.