GaN-on-Si semiconductor device structures for high current/ high voltage lateral GaN transistors and methods of fabrication thereof

Abstract

A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN transistors. A plurality of conventional GaN device structures comprising GaN epi-layers are fabricated on a silicon substrate (GaN-on-Si die). After processing of on-chip interconnect layers, a trench structure is defined around each die, through the GaN epi-layers and into the silicon substrate. A trench cladding is provided on proximal sidewalls, comprising at least one of a passivation layer and a conductive metal layer. The trench cladding extends over exposed surfaces of the GaN epi-layers, over the interface region with the substrate, and also over the exposed surfaces of the interconnect layers. This structure reduces risk of propagation of dicing damage and defects or cracks in the GaN epi-layers into active device regions. A metal trench cladding acts as a barrier for electro-migration of mobile ions.

The invention claimed is: 
     
       1. A wafer scale nitride semiconductor device structure comprising:
 a silicon substrate having formed thereon a GaN epi-layer stack for a plurality of GaN die, said plurality of GaN die being arranged as an array with dicing streets therebetween; 
 each of at least one of the GaN die comprising:
 a part of the GaN epi-layer stack, the GaN epi-layer stack comprising a GaN/AlGaN hetero-layer structure defining a two dimensional electron gas (2DEG) active layer for of a lateral GaN transistor; 
 source, drain and gate electrodes of the lateral GaN transistor being provided on a front-side an upper side of the GaN epi-layer stack over an active area of the GaN die, an inactive area of the GaN epi-layer stack surrounding said active area of each the GaN die, and; 
 an overlying interconnect structure that overlies a portion of the GaN epi-layer stack, the overlying interconnect structure comprising metallization and one or more dielectric layers;
 the metallization and dielectric layers, defining respective source, drain and gate connections and contact areas defining a source contact, a drain contact, and a gate contact of the lateral GaN transistor, the metallization electrically connecting and shorting the source contact with the source electrode, the drain contact with the drain electrode, and the gate contact with the gate electrode, 
 an upmost dielectric layer of the one or more dielectric layers having an upper surface that, together with an upper surface of the source and drain contacts, defines at least part of an upper surface of the overlying interconnect structure; and 
 
 a trench structure formed around a periphery of each the GaN die in said inactive area, the trench structure comprising a trench and a trench cladding; 
 the trench etched through layers of the overlying interconnect structure, through the GaN epi-layer stack, and into a surface region of the silicon substrate to a depth below an interface between the silicon substrate and the GaN epi-layer stack; 
 the trench structure further comprising a trench cladding, the trench cladding comprising a metal layer and an overlying passivation layer that overlies the metal layer, the trench cladding extending conformally over at least an inner sidewalls sidewall of the trench and sealing exposed surfaces of layers of the overlying interconnect structure, layers of the GaN epi-layer stack, and to thereby seal at least layers of the GaN epi-layer stack at the inner sidewall and to thereby seal at least the interface of between the silicon substrate and the GaN epi-layer stack and the silicon substrate at the inner sidewall, the trench cladding also extending conformally from the inner sidewall of the trench and over at least a portion of the upper surface of the overlying interconnect structure and contacting the source contact, 
 wherein the metal layer of the trench cladding is conductive and connects the silicon substrate to a the source contact area of the lateral GaN transistor such that the source contact is electrically connected and shorted to the silicon substrate through the metal layer. 
 
 
     
     
       2. The device structure of  claim 1 , wherein the trench structure is laterally spaced from the dicing street. 
     
     
       3. The device structure of  claim 1 , wherein the trench structure is laterally spaced from a scribe line of extends into the dicing street. 
     
     
       4. The device structure of  claim 1 , wherein the trench structure extends across the dicing street between adjacent GaN die. 
     
     
       5. The device structure of  claim 1 , wherein the GaN die further comprises a seal ring formed over the inactive region area of the GaN epi-layer stack and surrounding the lateral GaN transistor, the trench structure being formed between the seal ring and the dicing street, and wherein the metal layer of the trench cladding connects the silicon substrate to a metallization layer of the seal ring. 
     
     
       6. A nitride semiconductor device comprising:
 a GaN die comprising: 
 a silicon substrate and a GaN epi-layer stack formed thereon, the GaN epi-layer stack comprising a GaN/AlGaN hetero-layer structure defining a two dimensional electron gas (2DEG) active layer for of a lateral GaN transistor; 
 source, drain and gate electrodes of the lateral GaN transistor being provided on a front-side an upper side of the GaN epi-layer stack over an active area of the GaN die, an inactive area of the GaN epi-layer stack surrounding said active area of each the GaN die; and
 an overlying interconnect structure that overlies a portion of the GaN epi-layer stack, the overlying interconnect structure comprising metallization and one or more dielectric layers;
 the metallization and dielectric layers, defining respective source, drain and gate connections and contact areas defining a source contact, a drain contact, and a gate contact of the lateral GaN transistor, the metallization electrically connecting and shorting the source contact with the source electrode, the drain contact with the drain electrode, and the gate contact with the gate electrode, 
 an upmost dielectric layer of the one or more dielectric layers having an upper surface that, together with an upper surface of the source and drain contacts, defines at least part of an upper surface of the overlying interconnect structure; 
 
 a trench structure formed around a periphery of the GaN die, the trench structure comprising a trench and a trench cladding; 
 the trench etched through layers of the overlying interconnect structure, through layers of the GaN epi-layer stack, and into a surface region of the silicon substrate to a depth below the interface between the silicon substrate and the GaN epi-layer stack; 
 the trench structure further comprising a trench cladding, the trench cladding comprising a conductive metal layer and an overlying passivation layer that overlies the metal layer, the trench cladding extending conformally over at least an inner sidewalls sidewall of the trench and sealing exposed surfaces of layers of the interconnect structure, layers of the GaN epi-layer stack, and to thereby seal at least layers of the GaN epi-layer stack at the inner sidewall and to thereby seal at least the interface of between the silicon substrate and the GaN epi-layer stack and the silicon substrate at the inner sidewall, the trench cladding also extending conformally from the inner sidewall of the trench and over at least a portion of the upper surface of the overlying interconnect structure and contacting the source contact, 
 wherein the conductive metal layer of the trench cladding connects the silicon substrate to a the source contact area of the lateral GaN transistor such that the source contact is electrically connected and shorted to the silicon substrate through the conductive metal layer. 
 
 
     
     
       7. The device of  claim 6 , wherein the trench structure is laterally spaced from edges of the GaN die. 
     
     
       8. The device of  claim 6 , wherein the trench structure extends to edges of the GaN die. 
     
     
       9. The device of  claim 6 , wherein the GaN die further comprises a seal ring formed over the inactive region area of the GaN epi-layer stack and surrounding the lateral GaN transistor, the trench structure being formed between the seal ring and edges of the GaN die, and wherein the conductive metal layer of the trench cladding connects the silicon substrate to a metallization layer of the seal ring. 
     
     
       10. The device structure of  claim 6 , wherein the lateral GaN transistor comprises a plurality of transistor islands of a multi-island transistor, and further comprising a plurality of trenches dividing the active device area of the transistor into a plurality of areas, each of said plurality of areas accommodating a plurality of transistor islands. 
     
     
       11. The device structure of  claim 6 , wherein the lateral GaN transistor comprises a plurality of transistor islands of a multi-island transistor, and further comprising a plurality of trenches dividing the active device area of the transistor into a plurality of areas, each of said plurality of areas accommodating an individual transistor island. 
     
     
       12. A method of fabrication of a wafer scale nitride semiconductor device structureas defined in  claim 6 , comprising steps of:
 providing the a silicon substrate having formed thereon a GaN epi-layer structure stack for a plurality of GaN die, the plurality of GaN die being arranged as an array with dicing streets therebetween; 
 each of at least one of the GaN die comprising:
 a part of the GaN epi-layer stack, the GaN epi-layer stack comprising thea GaN/AlGaN hetero-layer structure defining the two dimensional electron gas (2DEG) active layer forof the lateral GaN transistor; 
 the source, drain and gate electrodes of the lateral GaN transistor being provided on the front-side an upper side of the GaN epi-layer stack over the active area of the GaN die, the inactive area of the GaN epi-layer stack surrounding said active area of each the GaN die; and 
 the an overlying interconnect structure, that overlies a portion of the GaN epilayer stack, the overlying interconnect structure comprising metallization and one or more dielectric layers;
 the metallization and dielectric layers, defining respective the source, drain and gate connections and contact areas defining a source contact, a drain contact, and a gate contact of the lateral GaN transistor, the metallization electrically connecting and shorting the source contact with the source electrode, the drain contact with the drain electrode, and the gate contact with the gate electrode, 
 an upmost dielectric layer of the one or more dielectric layers having an upper surface that, together with an upper surface of the source and drain contacts, defines at least part of an upper surface of the overlying interconnect structure; and 
 
 
 providing stress relief prior to dicing, comprising etching thea trench structure around all sides of each GaN die, the trench structure extending through the one or more layers of the overlying interconnect structure, through the layers of the GaN epi-layer stack, and into the surface region of the silicon substrate to the depth below the interface of the GaN epi-layer stack and the silicon substrate, the trench structure being laterally spaced from a dicing street of each edge of the GaN die; 
 providing the a trench cladding comprising the conductive metal layer and the overlying passivation layer, the trench cladding extending conformally over at least the inner sidewalls of the trench structure and sealing at least the exposed surfaces of the overlying interconnect structure, the layers of the GaN epi-layer stack, and the interface of the GaN epi-layer stack and the silicon substrate; and wherein the conductive metal layer of the trench cladding connects the silicon substrate to the source contact area of the lateral GaN transistor such that the source contact is electrically connected and shorted to the silicon substrate through the metal layer. 
 
     
     
       13. The method of  claim 12 , wherein etching the trench structure comprises:
 masking at least active areas of each GaN die and part of a surrounding inactive region exposing areas to be trenched; 
 in said areas, performing a sequence of dry etching steps comprising: 
 removing layers within the trench extending over the GaN epi-layer stack of the overlying interconnect structure, 
 removing the layers of the GaN epi-stack within the trench epi-layer stack, and 
 removing the surface region of the silicon substrate within the trench to the depth below the interface of the GaN epi-layer stack epi-layers and the silicon substrate. 
 
     
     
       14. The method of  claim 12 , further comprising dicing the silicon substrate along scribe lines laterally spaced from each trench along the dicing streets to singulate the plurality of GaN die. 
     
     
       15. The method of claim  12  14, wherein dicing comprises any one of sawing, laser ablation, plasma dicing, stealth dicing, laser induced splitting/cleaving, and a combination thereof. 
     
     
       16. The method of  claim 12 , wherein providing the conductive metal layer of the trench cladding comprises providing a metal barrier layer against electro-migration of contaminant ions. 
     
     
       17. The device of claim 6, wherein the overlying passivation layer of the trench cladding comprises at least one of a layer of a dielectric oxide and a layer of a dielectric nitride. 
     
     
       18. A wafer scale nitride semiconductor device structure comprising: a silicon substrate having formed thereon a GaN epi-layer stack for a plurality of GaN die, said plurality of GaN die being arranged as an array with dicing streets therebetween;
 each of at least one of the GaN die comprising:
 an area of the GaN epi-layer stack, the GaN epi-layer stack comprising a GaN/AlGaN hetero-layer structure defining a two-dimensional electron gas (2DEG) active layer of a lateral GaN transistor; 
 source, drain and gate electrodes of the lateral GaN transistor being provided on an upper side of the GaN epi-layer stack over an active area of the GaN die, an inactive area of the GaN epi-layer stack surrounding said active area of the GaN die; 
 an overlying structure that overlies a portion of the GaN epi-layer stack, the overlying structure comprising metallization and one or more dielectric layers,
 the metallization defining a source contact, a drain contact, and a gate contact of the lateral GaN transistor, the metallization electrically connecting and shorting the source contact with the source electrode, the drain contact with the drain electrode, and the gate contact with the gate electrode, 
 the one or more dielectric layers defining respective source, drain and gate connections and contact areas, 
 the metallization and the one or more dielectric layers defining a seal ring formed on the inactive area of the GaN die, the seal ring surrounding the active area of the GaN die; and 
 
 a trench formed around a periphery of the GaN die in said inactive area, the trench surrounding the seal ring and laterally spaced from the seal ring; the trench being etched through the one or more dielectric layers of the overlying structure, through the GaN epi-layer stack, and into a surface region of the silicon substrate to a depth below an interface between the silicon substrate and the GaN epi-layer stack; and 
 at least one layer of dielectric extending from the active area over the seal ring, and into the trench to form a dielectric trench cladding extending conformally over at least inner sidewalls of the trench and sealing at least surfaces of dielectric layers of the overlying structure, layers of the GaN epi-layer stack, and the interface of the GaN epi-layer stack and the silicon substrate. 
   
     
     
       19. The device structure of claim 18, wherein the at least one layer of dielectric of the dielectric trench cladding comprises at least one of a dielectric oxide and a dielectric nitride. 
     
     
       20. The device structure of claim 18, wherein the at least one layer of dielectric of the dielectric trench cladding comprises a layer of silicon dioxide and an overlying passivation layer of silicon nitride. 
     
     
       21. The device structure of claim 18, wherein the trench is laterally spaced from the dicing streets between adjacent GaN die. 
     
     
       22. The device structure of claim 18, wherein the trench extends across dicing streets between adjacent GaN die. 
     
     
       23. A nitride semiconductor device comprising:
 a GaN die comprising:   a silicon substrate and a GaN epi-layer stack formed thereon, the GaN epi-layer stack comprising a GaN/AlGaN hetero-layer structure defining a two-dimensional electron gas (2DEG) active layer of a lateral GaN transistor;   source, drain and gate electrodes of the lateral GaN transistor being provided on an upper side of the GaN epi-layer stack over an active area of the GaN die, an inactive area of the GaN epi-layer stack surrounding said active area of the GaN die;
 an overlying structure that overlies a portion of the GaN epi-layer stack, the overlying structure comprising metallization and one or more dielectric layers:
 the metallization defining a source contact, a drain contact, and a gate contact of the lateral GaN transistor, the metallization electrically connecting and shorting the source contact with the source electrode, the drain contact with the drain electrode, and the gate contact with the gate electrode, 
 the one or more dielectric layers defining respective source, drain and gate connections and contact areas, 
 the metallization and the one or more dielectric layers defining a seal ring formed on the inactive area of the GaN die, the seal ring surrounding the active area of the GaN die; 
 
 a trench formed around a periphery of the GaN die, the trench surrounding the seal ring, the trench being etched through the one or more dielectric layers of the overlying structure, through layers of the GaN epi-layer stack, and into a surface region of the silicon substrate to a depth below an interface between the silicon substrate and the GaN epi-layer stack; and 
 at least one layer of dielectric extending from the active area, over the seal ring, and into the trench to form a dielectric trench cladding extending conformally over at least inner sidewalls of the trench and sealing at least surfaces of dielectric layers of the overlying structure, layers of the GaN epi-layer stack, and the interface of the GaN epi-layer stack and the silicon substrate. 
   
     
     
       24. The nitride semiconductor device of claim 23, wherein the at least one layer of dielectric of the dielectric trench cladding comprises at least one of a dielectric oxide and a dielectric nitride. 
     
     
       25. The nitride semiconductor device of claim 23, wherein the at least one layer of dielectric of the dielectric trench cladding comprises a layer of silicon dioxide and an overlying passivation layer of silicon nitride. 
     
     
       26. The nitride semiconductor device of claim 23, wherein the trench extends around the periphery of the GaN die, spaced from diced edges of the GaN die. 
     
     
       27. The nitride semiconductor device of claim 23, wherein the trench extends to diced edges of the GaN die. 
     
     
       28. A method of fabricating a wafer scale nitride semiconductor device, comprising steps of:
 providing a silicon substrate having formed thereon a GaN epi-layer stack for a plurality of GaN die arranged as an array with dicing streets therebetween;   each of at least one of the GaN die comprising:
 an area of the GaN epi-layer stack comprising a GaN/AlGaN hetero-layer structure defining a two-dimensional electron gas (2DEG) active layer of a lateral GaN transistor; 
 source, drain and gate electrodes of the lateral GaN transistor being provided on an upper side of the GaN epi-layer stack over an active area of the GaN die, an inactive area of the GaN epi-layer stack surrounding said active area of the die; 
 an overlying structure that overlies a portion of the GaN epi-layer stack, the overlying structure comprising metallization and one or more dielectric layers;
 the metallization defining a source contact, a drain contact, and a gate contact of the lateral GaN transistor, the metallization electrically connecting and shorting the source contact with the source electrode, the drain contact with the drain electrode, and the gate contact with the gate electrode, 
 the one or more dielectric layers defining respective source, drain and gate connections and contact areas, 
 the metallization and the one or more dielectric layers defining a seal ring formed on the inactive area and surrounding the active area of the die, and the dielectric layers of the overlying structure extending over the inactive area; 
 
   providing stress relief prior to dicing, comprising etching a trench around a periphery of each GaN die, the trench extending through the one or more dielectric layers of the overlying structure, through layers of the GaN epi-layer stack, and into the surface region of the silicon substrate to a depth below an interface of the GaN epi-layer stack and the silicon substrate, the trench surrounding the seal ring, between the seal ring and a dicing street of each edge of the GaN die; and   providing at least one layer of dielectric extending from the active area, over the seal ring, and into the trench to form a dielectric trench cladding extending conformally over at least inner sidewalls of the trench and sealing at least surfaces of the overlying structure, the layers of the GaN epi-layer stack, and the interface of the GaN epi-layer stack and the silicon substrate.   
     
     
       29. The method of claim 28, wherein said trench around the periphery of each GaN die is laterally spaced from the dicing streets or extends across the dicing streets, and comprising dicing along said dicing streets to singulate the plurality of GaN die, wherein dicing comprises any one of sawing, laser ablation, plasma dicing, stealth dicing, laser induced splitting/cleaving, and a combination thereof. 
     
     
       30. The method of claim 28, wherein etching the trench structure comprises:
 masking at least active areas of each GaN die and part of a surrounding inactive area exposing areas to be trenched;   in said areas, performing a sequence of dry etching steps comprising:   removing layers of the overlying structure,   removing the GaN epi-layer stack, and   removing the surface region of the silicon substrate to the depth below the interface of the GaN epi-layer stack and the silicon substrate,   providing at least one layer of dielectric extending from the active area, over the seal ring, and into the trench to form a dielectric trench cladding extending conformally over inner sidewalls of the trench and sealing surfaces of the overlying structure, the layers of the GaN epi-layer stack, and the interface of the GaN epi-layer stack and the silicon substrate.