Semiconductor device and production method thereof

Abstract

A semiconductor device and a production method thereof capable of reducing warps of a semiconductor wafer when packaging at a wafer level in a SiP type semiconductor device, is configured that an insulating layer is formed by stacking a plurality of resin layers on a semiconductor chip formed with an electronic circuit, wiring layers are buried in the insulating layer and electrically connected to electrodes, and formation areas of the plurality of resin layers become gradually smaller from an area of an upper surface of the semiconductor chip as they get farther from the semiconductor chip, so that a side surface and an upper surface of each of the resin layers and the upper surface of the semiconductor chip form a stepwise shape.

What is claimed is: 
     
       1. A semiconductor device, comprising:
 a semiconductor chip with a built-in electronic circuit, having electrodes formed on a surface thereof that are taken out from the electronic circuit; 
 an insulating layer formed of a plurality of resin layers stacked on the semiconductor chip; and 
 a wiring layer formed so as to be electrically connected to the electrodes and buried in the insulating layer; wherein 
 the plurality of the resin layers is formed, so that as the layers get farther from the semiconductor chip, their formation areas become gradually smaller from an area of an upper surface of the semiconductor chip, and 
 a side surface and an upper surface of each of the resin layers and the upper surface of the semiconductor chip form a stepwise shape, wherein widths of exposed upper surfaces of the resin layers at the stepwise shaped portion are 5 μm or more in the plurality of the resin layers. 
 
     
     
       2. The semiconductor device as set forth in  claim 1 , wherein widths of exposed upper surfaces of the resin layers at the stepwise shaped portion are 5 μm or more in the plurality of the resin layers. 
     
     
       3. The semiconductor device as set forth in  claim 1 , wherein further comprising an electronic element and/or a another semiconductor chip are formed by being buried in the insulating layer so as to be electrically connected to the wiring layer. 
     
     
       4. A semiconductor device, comprising:
 a semiconductor chip with a built-in electronic circuit, having electrodes formed on a surface thereof that are taken out from the electronic circuit;   an insulating layer formed of a plurality of resin layers stacked on the semiconductor chip; and   a wiring layer formed so as to be electrically connected to the electrodes and buried in the insulating layer; wherein   the plurality of the resin layers is formed, so that as the layers get farther from the semiconductor chip, their formation areas become gradually smaller from an area of an upper surface of the semiconductor chip, and   a side surface and an upper surface of each of the resin layers and the upper surface of the semiconductor chip form a stepwise shape, wherein an electronic element and/or another semiconductor chip are formed by being buried in the insulating layer so as to be electrically connected to the wiring layer.   
     
     
       5. A semiconductor device, comprising:
 a semiconductor chip with a built-in electronic circuit, having electrodes formed on a surface thereof that are taken out from the electronic circuit;   an insulating layer formed of a plurality of resin layers stacked on the semiconductor chip; and   a wiring layer formed so as to be electrically connected to the electrodes and buried in the insulating layer; wherein   the plurality of the resin layers is formed, so that as the layers get farther from the semiconductor chip, their formation areas become gradually smaller from an area of an upper surface of the semiconductor chip, and   a side surface and an upper surface of each of the resin layers and the upper surface of the semiconductor chip form a stepwise shape, wherein   the plurality of resin layers includes a first resin layer having a tapered edge.   
     
     
       6. The semiconductor device as set forth in claim 5, wherein:
 the plurality of resin layers includes a second resin layer, the second resin layer have a smaller formation area than the first resin layer.   
     
     
       7. The semiconductor device as set forth in claim 6, wherein
 a ratio of a thickness of the first resin layer to a distance, D 1 , from an outer edge of the first resin layer to an outer edge of the second resin layer being 2 or less.   
     
     
       8. The semiconductor device as set forth in claim 6, wherein
 a distance from an outer edge of the first resin layer to an outer edge of the second resin layer being 5 μm or more.   
     
     
       9. The semiconductor device as set forth in claim 5, wherein
 a distance from an outermost edge of the semiconductor chip to an adjacent portion of the first resin layer being at least 10 μm.   
     
     
       10. The semiconductor device as set forth in claim 9, wherein
 the distance from the outermost edge of the semiconductor chip to the adjacent portion of the first resin layer being at most 39 μm.   
     
     
       11. The semiconductor device as set forth in claim 6, wherein
 in at least one location, a film thickness of at least one of the first resin layer and the second resin layer being substantially 10 μm.   
     
     
       12. The semiconductor device as set forth in claim 5, wherein
 the first resin layer being at least one of polymide, epoxy and/or acrylic.   
     
     
       13. The semiconductor device as set forth in claim 5, further comprising:
 a buffer layer disposed between the upper surface of the semiconductor chip and the plurality of resin layers.   
     
     
       14. The semiconductor device as set forth in claim 5, wherein
 an aggregate thickness of the plurality of resin layers for at least one portion of the plurality of layers is 50 μm or less.   
     
     
       15. The semiconductor device as set forth in claim 5, wherein
 a length of at least one side surface of the semiconductor chip being 3 mm or less.   
     
     
       16. The semiconductor device as set forth in claim 5, further comprising:
 a seed layer disposed between the wiring layer and the upper surface of the semiconductor chip, and portions of the seed layer being in electrical contact with portions of the wiring layer.   
     
     
       17. The semiconductor device as set forth in claim 16, wherein
 the seed layer having a thickness of in an inclusive range of 160 nm through 600 nm.   
     
     
       18. The semiconductor device as set forth in claim 7, wherein
 a distance from an outermost edge of the semiconductor chip to an adjacent portion of the first resin layer being at least 10 μm.   
     
     
       19. The semiconductor device as set forth in claim 18, wherein
 the distance from the outermost edge of the semiconductor chip to the adjacent portion of the first resin layer being at most 39 μm.   
     
     
       20. The semiconductor device as set forth in claim 19, further comprising:
 a buffer layer disposed between the upper surface of the semiconductor chip and the plurality of resin layers.   
     
     
       21. The semiconductor device as set forth in claim 20, wherein
 an aggregate thickness of the plurality of resin layers for at least one portion of the plurality of layers is 50 μm or less.   
     
     
       22. The semiconductor device as set forth in claim 21, further comprising:
 a seed layer disposed between the wiring layer and the upper surface of the semiconductor chip, and portions of the seed layer being in electrical contact with portions of the wiring layer.   
     
     
       23. The semiconductor device as set forth in claim 22, wherein
 the seed layer having a thickness of in an inclusive range of 160 nm through 600 nm.   
     
     
       24. The semiconductor device as set forth in claim 1, wherein:
 the plurality of resin layers includes a second resin layer, the second resin layer have a smaller formation area than the first resin layer.   
     
     
       25. The semiconductor device as set forth in claim 24, wherein
 a ratio of a thickness of the first resin layer to a distance, D 1 , from an outer edge of the first resin layer to an outer edge of the second resin layer being 2 or less.   
     
     
       26. The semiconductor device as set forth in claim 1, wherein
 a distance from an outermost edge of the semiconductor chip to an adjacent portion of the first resin layer being at least 10 μm.   
     
     
       27. The semiconductor device as set forth in claim 26, wherein
 the distance from the outermost edge of the semiconductor chip to the adjacent portion of the first resin layer being at most 39 μm.   
     
     
       28. The semiconductor device as set forth in claim 27, further comprising:
 a buffer layer disposed between the upper surface of the semiconductor chip and the plurality of resin layers.   
     
     
       29. The semiconductor device as set forth in claim 28, wherein
 an aggregate thickness of the plurality of resin layers for at least one portion of the plurality of layers is 50 μm or less.   
     
     
       30. The semiconductor device as set forth in claim 29, further comprising:
 a seed layer disposed between the wiring layer and the upper surface of the semiconductor chip, and portions of the seed layer being in electrical contact with portions of the wiring layer.   
     
     
       31. The semiconductor device as set forth in claim 30, wherein
 the seed layer having a thickness of in an inclusive range of 160 nm through 600 nm.   
     
     
       32. The semiconductor device as set forth in claim 4, wherein:
 the plurality of resin layers includes a second resin layer, the second resin layer have a smaller formation area than the first resin layer.   
     
     
       33. The semiconductor device as set forth in claim 32, wherein a ratio of a thickness of the first resin layer to a distance, D 1 , from an outer edge of the first resin layer to an outer edge of the second resin layer being 2 or less. 
     
     
       34. The semiconductor device as set forth in claim 4, wherein
 a distance from an outermost edge of the semiconductor chip to an adjacent portion of the first resin layer being at least 10 μm.   
     
     
       35. The semiconductor device as set forth in claim 34, wherein
 the distance from the outermost edge of the semiconductor chip to the adjacent portion of the first resin layer being at most 39 μm.   
     
     
       36. The semiconductor device as set forth in claim 35, further comprising:
 a buffer layer disposed between the upper surface of the semiconductor chip and the plurality of resin layers.   
     
     
       37. The semiconductor device as set forth in claim 36, wherein
 an aggregate thickness of the plurality of resin layers for at least one portion of the plurality of layers is 50 μm or less.   
     
     
       38. The semiconductor device as set forth in claim 37, further comprising:
 a seed layer disposed between the wiring layer and the upper surface of the semiconductor chip, and portions of the seed layer being in electrical contact with portions of the wiring layer.   
     
     
       39. The semiconductor device as set forth in claim 38, wherein
 the seed layer having a thickness of in an inclusive range of 160 nm through 600 nm.