Device and system including adaptive repair circuit

Abstract

A device, system, and/or method includes an internal circuit configured to perform at least one function, an input-output terminal set and a repair circuit. The input-output terminal set includes a plurality of normal input-output terminals connected to an external device via a plurality of normal signal paths and at least one repair input-output terminal selectively connected to the external device via at least one repair signal path. The repair circuit repairs at least one failed signal path included in the normal signal paths based on a mode signal and fail information signal, where the mode signal represents whether to use the repair signal path and the fail information signal represents fail information on the normal signal paths. Using the repair circuit, various systems adopting different repair schemes may be repaired and cost of designing and manufacturing the various systems may be reduced.

What is claimed is: 
     
       1. A memory system comprising:
 a memory controller; 
 a memory device comprising:
 N number of input-output terminals and a repair input-output terminal disposed in an order of first to Nth input-output terminals and the repair input-output terminal, the N being a natural integer; and 
 an adaptive repair circuit configured to perform a first repair mode in response to a first mode signal and a first fail information, and to perform a second repair mode in response to a second mode signal and a second fail information; and 
 
 an interposer including a plurality of signal paths disposed in accordance with the order of the input-output terminals, and each of the plurality of signal paths connecting each of the input-output terminals to a corresponding terminal of the memory controller, wherein, 
 in the first repair mode, when the first fail information indicates that jth signal path connected to jth input-output terminal has failed, j being a natural integer smaller than N, the adaptive repair circuit is configured to replace each of jth to N−1th signal paths with each of j+1th to Nth signal paths respectively, and 
 in the second repair mode, when the second fail information indicates that kth signal path connected to kth input-output terminal failed, k being a natural integer equal to or smaller than N, the adaptive repair circuit is configured to replace each of the kth to Nth signal paths with each of k+1th to Nth signal paths and a repair signal path which is connected to the repair input-output terminal respectively. 
 
     
     
       2. The memory system of  claim 1 , wherein
 the first to N−1th input-output terminals are main input-output terminals; 
 the Nth input-output terminal is a sub input-output terminal; and 
 in the first repair mode, the sub input-output terminal is not electrically connected to any of the plurality of signal paths, and 
 in the second repair mode, the sub input-output terminal is connected to the repair signal path. 
 
     
     
       3. The memory system of  claim 2 , wherein
 the main input-output terminals are configured to transfer main signals for main operation of the memory device; 
 the main operation is one of a read operation and a write operation; and 
 the sub input-output terminal is configured to transfer a sub signal for sub operation of the memory device, the sub operation and the sub signal are data bus inversion operation and a data bus inversion signal respectively. 
 
     
     
       4. The memory system of  claim 1 , wherein, in the first repair mode, the first to j−1th input-output terminals are connected to the first to j−1th signal paths respectively, and in the second repair mode, the first to k−1th input-output terminals are connected to the first to k−1th signal paths respectively. 
     
     
       5. The memory system of  claim 1 , wherein the memory controller is configured to provide the first fail information and the second fail information. 
     
     
       6. The memory system of  claim 5 , wherein the memory controller includes a built-in self-test (BIST) circuit configured to generate the first fail information and the second fail information. 
     
     
       7. The memory system of  claim 6 , wherein the BIST circuit is configured to test the plurality of signal paths connecting the memory controller and the memory device while rebooting the memory system to provide the first and/or second fail information. 
     
     
       8. The memory system of  claim 1 , wherein the memory controller and the memory device are mounted on the interposer. 
     
     
       9. The memory system of  claim 1 , wherein the memory system further includes a substrate on which the interposer in mounted. 
     
     
       10. The memory system of  claim 9 , wherein the memory system further includes a conductive bump formed on a lower surface of the substrate for connecting the memory system to an external device. 
     
     
       11. The memory system of  claim 1 , wherein the memory device comprising:
 a master chip; and 
 a slave chip stacked on the master chip, the slave chip configured to transfer and receive electrical signals to/from the master chip through through-silicon-vias (TSVs), and the slave chip including an internal circuit configured to perform at least one function. 
 
     
     
       12. The memory system of  claim 11 , wherein the adaptive repair circuit is included in the master chip. 
     
     
       13. The memory system of  claim 1 , further comprising:
 a mode register set configured to set each of the first mode signal and the second mode through a mode register set operation. 
 
     
     
       14. A memory system, comprising:
 a first sub system; 
 a second sub system comprising: 
 a plurality of input-output terminals disposed in an order of a first group of input-output terminals, a repair input-output terminal, and a second group of input-output terminals, the first group of input-output terminals including N number of input-output terminals disposed in an order of first to Nth input-output terminals and the second group of input-output terminals including M number of input-output terminals disposed in an order of first to Mth input-output terminals, the N and M being natural integers; and 
 an adaptive repair circuit configured to perform a repair operation in response to a fail information; and 
 an interposer including a first group of signal paths disposed in accordance with the order of the first group of input-output terminal and each of the first group of signal paths connecting each of the first group of input-output terminals of the second sub system to corresponding terminal terminals of the first sub system, a repair signal path connecting the repair input-output terminals of the second sub system to corresponding terminal of the first sub system, and a second group of signal paths disposed in accordance with the order of the second group of input-output terminals and each of the second group of signal paths connecting each of the second group of input-output terminals of the second sub system to corresponding terminal terminals of the first sub system, wherein, 
 when the fail information indicates that jth signal path in the first group of signal paths failed, the adaptive repair circuit is configured to replace each of the jth to Nth input-output terminals of the first group of input-output terminals with each of j+1th to Nth signal paths of the first group of signal paths and the repair signal path respectively, and 
 when the fail information indicates that kth signal path in the second group of signal paths failed, the adaptive repair circuit is configured to replace each of the kth to Mth input-output terminals of the second group of input-output terminals to each of k+1th to Mth signal paths of the second group of signal paths and the repair signal path respectively, j and k are natural integers, and equal to or smaller than N and M respectively, and 
 the repair signal path is located between the first group of signal paths and the second group of signal paths. 
 
     
     
       15. The memory system of  claim 14 , wherein the N and the M are the same. 
     
     
       16. The memory system of  claim 14 , wherein
 when the fail information indicates that jth signal path among the first group of signal path failed, the adaptive repair circuit is further configured to connect each of the first to j−1th input-output terminals of the first group of input-output terminals to each of first to j−1th signal paths of the first group of signal paths respectively; and 
 when the fail information indicates that kth signal path in the second group of signal paths failed, the adaptive repair circuit is further configured to replace each of the first to k−1th input-output terminals of the second group of input-output terminals to each of first to k−1th signal paths of the second group of signal paths respectively. 
 
     
     
       17. The memory system of  claim 16 , wherein the repair signal path is located between the first group of signal paths and the second group of signal paths. 
     
     
       18. The memory system of claim  17   14 , wherein the repair signal path is shared by both the Nth input-output terminal of the first group of input-output terminals and the Mth input-output terminal of the second group of input-output terminals. 
     
     
       19. The memory system of  claim 14 , wherein the first sub system and the second sub system are a master chip and a slave chip respectively, the slave chip is stacked on the master chip and configured to transfer and receive electrical signals to/from the master chip through through-silicon-vias (TSVs). 
     
     
       20. The memory system of  claim 19 , wherein the adaptive repair circuit is included in the master chip. 
     
     
       21. A memory system, comprising:
 a memory controller;   a memory device including an adaptive repair circuit, the adaptive repair circuit configured to receive first fail information during a first repair mode and to receive second fail information during a second repair mode; and   an interposer including a plurality of normal signal paths and at least one repair signal path, the plurality of normal signal paths comprising a plurality of main signal paths and a sub signal path, each of the plurality of normal signal paths and the at least one repair signal path being configured to connect the memory controller and the memory device, wherein   in the first repair mode, the adaptive repair circuit is configured to repair a failed signal path using the sub signal path based on the first fail information, and   in the second repair mode, the adaptive repair circuit is configured to repair the failed signal path using the repair signal path based on the second fail information,   the plurality of main signal paths are configured to transfer main signals for main operation of the memory device, the main operation being one of a read operation and a write operation, and   the sub signal path is configured to transfer a sub signal for sub operation of the memory device, the sub operation and the sub signal being a data bus inversion operation and a data bus inversion signal respectively.   
     
     
       22. The memory system of  claim 21 , wherein the data bus inversion operation based on the sub signal path is not performed when the failed signal path is repaired in the first repair mode. 
     
     
       23. The memory system of  claim 21 , wherein the adaptive repair circuit is configured to replace the sub signal path with the repair signal path in the second repair mode. 
     
     
       24. The memory system of  claim 21 , wherein each of the first fail information and the second fail information identifies the failed signal path among the plurality of the normal signal paths. 
     
     
       25. The memory system of  claim 21 , wherein the memory controller is configured to provide the first fail information in the first repair mode and the second fail information in the second repair mode to the memory device. 
     
     
       26. The memory system of  claim 21 , wherein the memory controller includes a built-in self-test (BIST) circuit configured to generate the first fail information and the second fail information. 
     
     
       27. The memory system of  claim 26 , wherein the built-in self-test circuit is configured to test the plurality of normal signal paths connecting the memory controller and the memory device in response to rebooting of the memory system to provide the first fail information and the second fail information. 
     
     
       28. The memory system of  claim 21 , wherein the memory controller and the memory device are mounted on the interposer. 
     
     
       29. The memory system of  claim 21 , further comprising:
 a base substrate on which the interposer in mounted.   
     
     
       30. The memory system of  claim 29 , further comprising:
 a conductive bump formed on a lower surface of the base substrate, the conductive bump configured to connect the memory system to an external device.   
     
     
       31. The memory system of  claim 21 , wherein
 the plurality of normal signal paths are divided into a plurality of groups; and   one repair signal path is assigned to two groups of the plurality of groups.   
     
     
       32. The memory system of  claim 21 , wherein the failed signal path is one of the plurality of main signal paths. 
     
     
       33. A memory device comprising:
 an input-output terminal set including a plurality of normal input-output terminals and a repair input-output terminal, the plurality of normal input-output terminals being connected to an external device via a plurality of main signal paths and a sub signal path, and the repair input-output terminal being selectively connected to the external device via a repair signal path; and   an adaptive repair circuit configured to repair a failed signal path based on a repair mode and fail information, wherein
 in a first repair mode, the adaptive repair circuit is configured to repair the failed signal path using the sub signal path, and 
 in a second repair mode, the adaptive repair circuit is configured to repair the failed signal path using the repair signal path, 
   the plurality of main signal paths are configured to transfer main signals for main operation of the memory device, the main operation being one of a read operation and a write operation, and   the sub signal path is configured to transfer a sub signal for sub operation of the memory device, the sub operation and the sub signal being a data bus inversion operation and a data bus inversion signal respectively.   
     
     
       34. The memory device of  claim 33 , wherein, if one of the plurality of main signal paths is repaired using the sub signal path during the first repair mode, the memory device is configured to not perform the data bus inversion operation based on the sub signal path. 
     
     
       35. The memory device of  claim 34 , wherein the adaptive repair circuit is configured to replace the sub signal path with the repair signal path in the second repair mode. 
     
     
       36. The memory device of  claim 34 , wherein the fail information identifies the failed signal path among the plurality of the normal signal paths. 
     
     
       37. The memory device of  claim 34 , wherein the failed signal path is one of the plurality of main signal paths. 
     
     
       38. A memory device, comprising:
 a master chip, comprising,
 an input-output terminal set including a plurality of normal input-output terminals and a repair input-output terminal, the plurality of normal input-output terminals being connected to an external device via a plurality of main signal paths and a sub signal path, and the repair input-output terminal being selectively connected to the external device via a repair signal path, and 
 an adaptive repair circuit configured to repair a failed signal path based on a repair mode and fail information; and 
   a slave chip stacked on the master chip, the slave chip being configured to transfer and receive electrical signals to/from the master chip through through-silicon-vias (TSVs), and the slave chip including an internal circuit configured to perform at least one function,
 wherein,
 in a first repair mode, the adaptive repair circuit is configured to repair the failed signal path using the sub signal path, and 
 in a second repair mode, the adaptive repair circuit is configured to repair the failed signal path using the repair signal path, 
 
 the plurality of main signal paths are configured to transfer main signals for main operation of the memory device, the main operation being one of a read operation and a write operation, and 
 the sub signal path is configured to transfer a sub signal for sub operation of the memory device, the sub operation and the sub signal being a data bus inversion operation and a data bus inversion signal respectively.