Three dimensional semiconductor devices

Abstract

Three-dimensional semiconductor devices are provided. The three-dimensional semiconductor device includes a substrate, a buffer layer on the substrate. The buffer layer includes a material having an etching selectivity relative to that of the substrate. A multi-layer stack including alternating insulation patterns and conductive patterns is provided on the buffer layer opposite the substrate. One or more active patterns respectively extend through the alternating insulation patterns and conductive patterns of the multi-layer stack and into the buffer layer. Related fabrication methods are also discussed.

What is claimed is: 
     
       1. A semiconductor device comprising:
 a substrate; 
 a buffer layer on the substrate, the buffer layer comprising a material having an etching selectivity relative to that of the substrate; 
 a multi-layer stack comprising alternating insulation patterns and conductive patterns on the buffer layer opposite the substrate; and 
 one or more active patterns respectively extending through the alternating insulation patterns and conductive patterns of the multi-layer stack and into the buffer layer, wherein the plurality of one or more active patterns are electrically connected to the substrate, 
 wherein the one or more active patterns are confined above the substrate and respectively extend into the buffer layer to a uniform depth, 
 wherein the material of the buffer layer has a lower etch rate than that of the substrate, 
 wherein the buffer layer comprises a buried insulation layer on a surface of the substrate, and a semiconductor layer on the buried insulation layer opposite the substrate, and 
 wherein the one or more active patterns extend through the semiconductor layer and at least partially into the buried insulation layer. 
 
     
     
       2. The device of  claim 1 , wherein the active patterns are confined above the substrate and respectively extend into the buffer layer to a uniform depth. 
     
     
       3. The device of  claim 2 , wherein the material of the buffer layer has a lower etch rate than that of the substrate. 
     
     
       4. The device of  claim 3 , wherein the buffer layer comprises:
 a buried insulation layer on the surface of the substrate; and   a semiconductor layer on the buried insulation layer opposite the substrate,   wherein the active patterns extend through the semiconductor layer and at least partially into the buried insulation layer.   
     
     
       5. The device of claim  4   1 , wherein the active patterns extend completely through the buried insulation layer to contact the substrate. 
     
     
       6. The device of claim  4   1 , wherein a portion of the buried insulation layer separates the active patterns from the substrate. 
     
     
       7. The device of claim  4   1 , wherein openings in the semiconductor layer through which the active patterns extend are narrower than openings in the buried insulation layer into which the active patterns extend. 
     
     
       8. The device of claim  4   1 , wherein the semiconductor layer includes a doped region therein that defines a common source line, and wherein the common source line is insulated from the substrate by the buried insulation layer. 
     
     
       9. The device of claim  4   1 , wherein the active pattern comprises a first active layer on sidewalls of a trench extending through the multi-layer stack into the buffer layer and a second active layer on the first active layer, wherein the first active layer is confined above the buried insulation layer, and wherein the second active layer extends into the buried insulation layer. 
     
     
       10. The device of  claim 9 , wherein portions of the second active layer extend between the sidewalls of the trench and the first active layer. 
     
     
       11. A semiconductor device, comprising:
 a substrate; 
 a buffer layer on the substrate, the buffer layer comprising a material having an etching selectivity relative to that of the substrate, wherein the buffer layer comprises a carbon-containing polysilicon layer; 
 a multi-layer stack comprising alternating insulation patterns and conductive patterns on the buffer layer opposite the substrate; 
 one or more active patterns respectively extending through the alternating insulation patterns and conductive patterns of the multi-layer stack and into the buffer layer; and 
 an isolating pattern comprising an insulating material extending through the insulation patterns and conductive patterns of the multi-layer stack between adjacent ones of the active patterns, 
 wherein the isolating pattern and a doped region of the buffer layer overlap in plan view. 
 
     
     
       12. The device of  claim 11 , wherein the buffer layer comprises a carbon-containing polysilicon layer having has a lower etch rate than the substrate. 
     
     
       13. The device of  claim 11 , wherein the isolating pattern is closer to one of the adjacent ones of the active patterns than another. 
     
     
       14. The device of  claim 11 , wherein the conductive patterns comprise gate electrodes of a string of serially connected transistors having respective source and drain regions in the active pattern one or more active patterns. 
     
     
       15. The device of  claim 14 , wherein the semiconductor device comprises a NAND flash memory device, and further comprising:
 a bit line on the multi-layer stack opposite the substrate and electrically contacting the active patterns, 
 wherein the conductive patterns define selection lines and word lines of the memory device, and wherein the string of serially connected transistors comprise selection transistors and memory cell transistors serially connected between the selection transistors. 
 
     
     
       16. A three-dimensional semiconductor memory device comprising:
 a buffer layer on a substrate, wherein the buffer layer includes a material having an etch selectivity with respect to the substrate, and wherein the buffer layer includes a buried insulation layer on the substrate, and a semiconductor layer on the buried insulation layer opposite the substrate; 
 a plurality of conductive patterns and interlayer insulation patterns alternately stacked on the buffer layer, wherein the conductive patterns define selection lines and word lines of the memory device; 
 active patterns penetrating the conductive patterns and the interlayer insulation patterns to contact the buffer layer at a uniform depth, wherein the conductive patterns provide gate electrodes of a string of serially connected transistors having respective source and drain regions in the active pattern; 
 an isolating insulation pattern penetrating the conductive patterns and the interlayer insulation patterns between adjacent ones of the active patterns to contact a doped region of the buffer layer, wherein the doped region defines a common source line of the memory device; and 
 a bit line on the conductive patterns and the interlayer insulation patterns opposite the substrate and electrically contacting the active patterns. 
 
     
     
       17. The three-dimensional semiconductor memory device of  claim 16 , wherein the buffer layer includes:
 a buried insulation layer on the substrate; and   a semiconductor layer on the buried insulation layer opposite the substrate.   
     
     
       18. The three-dimensional semiconductor memory device of claim  17   16 , wherein lower portions of the active patterns are disposed in the buried insulation layer, and each of the lower portions of the active patterns has an anchor-shaped cross sectional view. 
     
     
       19. The three-dimensional semiconductor memory device of  claim 18 , wherein the common source line is disposed in the semiconductor layer. 
     
     
       20. The three-dimensional semiconductor memory device of  claim 19 , wherein a lateral distance between the isolating insulation pattern and one of the active patterns is different from a lateral distance between the isolating insulation pattern and another of the active patterns, and wherein the buried insulation layer surrounds the lower portions of the active patterns and has a nonlinear shape in plan view. 
     
     
       21. A semiconductor device comprising:
 a substrate;   a first buffer layer disposed on the substrate;   a second buffer layer disposed on the first buffer layer, each of the first buffer layer and the second buffer layer including a material having an etching selectivity relative to that of the substrate;   a multi-layer stack disposed on the second buffer layer, and including alternating insulation patterns and conductive patterns, the multi-layer stack being disposed opposite to the substrate with respect to each of the first buffer layer and the second buffer layer; and   one or more active patterns,   wherein each of the one or more active patterns extends through the alternating insulation patterns and conductive patterns of the multi-layer stack, and extends into the first buffer layer and the second buffer layer, and   the one or more active patterns are electrically connected to the substrate,   wherein an insulating pattern at least partially fills an inner space of the one or more active patterns,   wherein the inner space of the one or more active patterns includes a first part and a second part disposed on the first part, the first part and the second part are disposed in the first buffer layer and the second buffer layer, and a width of the first part of the inner space of the one or more active patterns is greater than a width of the second part of the inner space of the one or more active patterns.   
     
     
       22. The semiconductor device of  claim 21 , wherein the inner space of the one or more active patterns includes a third part disposed beneath the second part,
 the width of the first part of the inner space of the one or more active patterns is greater than a width of the third part of the inner space of the one or more active patterns.   
     
     
       23. The semiconductor device of  claim 21 , wherein the insulating pattern includes a first portion and a second portion disposed on the first portion,
 each of the first portion and the second portion of the insulating pattern is disposed in the first buffer layer and/or the second buffer layer, and   a width of the first portion of the insulating pattern is greater than a width of the second portion of the insulating pattern.   
     
     
       24. The semiconductor device of  claim 23 , wherein the insulating pattern further includes a third portion disposed beneath the first portion,
 the third portion of the insulating pattern is disposed in the first buffer layer and/or the second buffer layer, and   the width of the first portion of the insulating pattern is greater than a width of the third portion of the insulating pattern.   
     
     
       25. The semiconductor device of  claim 21 , wherein at least one of the first buffer layer and the second buffer layer includes oxide. 
     
     
       26. The semiconductor device of  claim 21 , wherein the first buffer layer includes a first space,
 a lower portion of the one or more active patterns is disposed in the first space of the first buffer layer,   the first space of the first buffer layer includes a first portion and a second portion disposed on the first portion, and   a width of the first portion of the first space of the first buffer layer is less than a width of the second portion of the first space of the first buffer layer.   
     
     
       27. The semiconductor device of  claim 26 , wherein the second buffer layer includes a second space through which the one or more active patterns extends, and
 a width of the second space of the second buffer layer is less than the width of the second portion of the first space of the first buffer layer.   
     
     
       28. The semiconductor device of  claim 21 , wherein the one or more active patterns is confined above the substrate. 
     
     
       29. The semiconductor device of  claim 21 , wherein the material included in each of the first buffer layer and the second buffer layer has a lower etch rate than that of the substrate. 
     
     
       30. A semiconductor device comprising:
 a substrate;   a buffer layer disposed on the substrate and including a material having an etching selectivity relative to that of the substrate;   a multi-layer stack disposed on the buffer layer, and including alternating insulation patterns and conductive patterns, the multi-layer stack being disposed opposite to the substrate with respect to the buffer layer;   one or more active patterns respectively extending through the alternating insulation patterns and conductive patterns of the multi-layer stack, and respectively extending into the buffer layer; and   an insulating pattern at least partially filling an inner space of the one or more active patterns,   wherein the one or more active patterns are electrically connected to the substrate, the insulating pattern includes a first portion and a second portion disposed on the first portion, each of the first portion and the second portion of the insulating pattern is disposed in the buffer layer, a width of the first portion of the insulating pattern is greater than a width of the second portion of the insulating pattern, and the buffer layer includes a first buffer layer and a second buffer layer disposed on the first buffer layer.   
     
     
       31. The semiconductor device of  claim 30 , wherein the insulating pattern further includes a third portion disposed beneath the first portion,
 the third portion of the insulating pattern is disposed in the buffer layer, and   the width of the first portion of the insulating pattern is greater than a width of the third portion of the insulating pattern.   
     
     
       32. The semiconductor device of  claim 30 , wherein the buffer layer includes oxide. 
     
     
       33. The semiconductor device of  claim 30 , wherein the buffer layer includes a space,
 a lower portion of the one or more active patterns is disposed in the space of the buffer layer,   the space of the buffer layer includes a first part, a second part disposed on the first part and a third part disposed on the second part,   a width of the first part of the space of the buffer layer is less than a width of the second part of the space of the buffer layer, and   the width of the second part of the space of the buffer layer is greater than a width of the third part of the space of the buffer layer.   
     
     
       34. The semiconductor device of  claim 30 , wherein the inner space of the one or more active patterns includes a first part, a second part disposed on the first part, and a third part disposed on the second part,
 a width of the first part of the inner space of the one or more active patterns is less than a width of the second part of the inner space of the one or more active patterns, and   the width of the second part of the inner space of the one or more active patterns is greater than a width of the third part of the inner space of the one or more active patterns.   
     
     
       35. The semiconductor device of  claim 30 , wherein the one or more active patterns extends through the second buffer layer and extends at least partially into the first buffer layer. 
     
     
       36. The semiconductor device of  claim 30 , wherein the one or more active patterns extends completely through the buffer layer to contact the substrate. 
     
     
       37. A semiconductor device comprising:
 a substrate;   a buffer layer disposed on the substrate and including a material having an etching selectivity relative to that of the substrate;   a multi-layer stack disposed on the buffer layer, and including alternating insulation patterns and conductive patterns, the multi-layer stack being disposed opposite to the substrate with respect to the buffer layer; and   one or more active patterns respectively extending through the alternating insulation patterns and conductive patterns of the multi-layer stack, and respectively extending into the buffer layer,   wherein the one or more active patterns are electrically connected to the substrate,   the buffer layer includes a first buffer layer and a second buffer layer disposed on the first buffer layer,   the buffer layer includes oxide, and includes a space,   a lower portion of the one or more active patterns is disposed in the space of the buffer layer,   the space of the buffer layer includes a first portion, a second portion disposed on the first portion and a third portion disposed on the second portion,   a width of the first portion of the space of the buffer layer is less than a width of the second portion of the space of the buffer layer, and   the width of the second portion of the space of the buffer layer is greater than a width of the third portion of the space of the buffer layer.   
     
     
       38. The semiconductor device of  claim 37 , wherein an inner space of the one or more active patterns includes a first part, a second part disposed on the first part, and a third part disposed on the second part,
 a width of the first part of the inner space of the one or more active patterns is less than a width of the second part of the inner space of the one or more active patterns, and   the width of the second part of the inner space of the one or more active patterns is greater than a width of the third part of the inner space of the one or more active patterns.   
     
     
       39. The semiconductor device of  claim 37 , wherein a portion of the buffer layer separates the one or more active patterns from the substrate. 
     
     
       40. The semiconductor device of  claim 37 , wherein an opening of an upper surface of the second buffer layer through which the one or more active patterns extends are narrower than an opening of an upper surface of the first buffer layer into which the one or more active patterns extends.