Integrated circuit device including vertical memory device and method of manufacturing the same

Abstract

In one embodiment, the semiconductor device includes a stack of alternating interlayer insulating layers and conductive layers on a substrate. Each of the conductive layers extends in a first direction less than a previous one of the conductive layers to define a landing portion of the previous one of the conductive layers. An insulating plug is in one of the conductive layers under one of the landing portions, and a contact plug extends from an upper surface of the one of the landing portions.

What is claimed is: 
     
       1. A method of manufacturing a semiconductor device, comprising:
 preparing a substrate comprising a cell array region and a word line contact region; 
 forming a stack of alternating first and second layers on the substrate, each of the second layers extending in a first direction less than a previous one of the second layers to define a landing portion of the previous one of the second layers in the word line contact region; 
 forming a first hole through at least one of a plurality of the first layers and at least one of a plurality of the second layers in the stack such that the first hole penetrates one of the landing portions; 
 etching the plurality of the first layers to widen portions of the first hole at least under respective ones of the plurality of the second layers; 
 forming a support insulating layer within the first hole including the widened portions; 
 exposing part of the landing portions by removing a bottom portion of the support insulating layer; and 
 forming contact plugs such that each of the contact plugs is in contact with a respective one of the landing portions. 
 
     
     
       2. The method of  claim 1 , further comprising:
 removing the second layers to form a second layer removal space; and 
 filling the second layer removal space with a conducting material to form conductive layers alternately stacked with the first layers. 
 
     
     
       3. The method of  claim 2 , wherein the first layers are interlayer insulating layers. 
     
     
       4. The method of  claim 3 , wherein the second layers are formed of a different insulating material than the first layers. 
     
     
       5. The method of  claim 1 , wherein the forming a first hole forms the first hole through an entirety of the stack. 
     
     
       6. The method of  claim 1 , wherein the forming a first hole forms the first hole through less than an entirety of the stack. 
     
     
       7. The method of  claim 1 , wherein the etching is a wet etching selective to the first layers. 
     
     
       8. The method of  claim 1 , wherein the forming contact plugs forms one of the contact plugs on the landing portion including the first hole such that the one of the contact plugs covers the first hole. 
     
     
       9. The method of  claim 8 , wherein the one of the contact plugs fills at least a portion of the first hole. 
     
     
       10. The method of  claim 1 , wherein the first layers are interlayer insulating layers. 
     
     
       11. The method of  claim 10 , wherein the second layers are formed of a different insulating material than the first layers. 
     
     
       12. A method of manufacturing a semiconductor device, comprising:
 preparing a substrate comprising a cell array region and a word line contact region; 
 forming a stack of alternating interlayer insulating layers and sacrificial layers on the substrate, each of the sacrificial layers extending in a first direction less than a previous one of the sacrificial layers to define a first landing portion of the previous one of the sacrificial layers in the word line contact region; 
 removing (i) a portion of the first landing portion of each of the sacrificial layers and (ii) portions of the interlayer insulating layers at least above and below remaining portions of each of the first landing portions of the sacrificial layers, to define a plurality of recesses; 
 forming a support insulating layer within the plurality of recesses; 
 forming a word line cut trench exposing the substrate in the cell array region;  
 removing the sacrificial layers exposed through the word line cut trench to form a sacrificial layer removal space; 
 filling the sacrificial layer removal space with a conducting material to form gate electrode layers alternately stacked with the interlayer insulating layers; 
 exposing part of each of the first landing portions by removing a bottom portion of the support insulating layer; and 
 forming contact plugs such that each of the contact plugs is in contact with a respective one of the first landing portions. 
 
     
     
       13. A method comprising:
 forming an alternating stack of insulating layers and sacrificial layers, the alternating stack including stepped surfaces in a contact region on a substrate;   forming a first insulating portion on the stepped surfaces of the alternating stack;   forming contact holes to pass through the first insulating portion and the alternating stack;   forming sacrificial structures in the contact holes, respectively;   forming a word line cut trench to pass through the alternating stack;   removing the sacrificial layers exposed through the word line cut trench;   forming a plurality of gate electrodes by filling spaces at which the sacrificial layers have been removed with a conductive material; and   replacing a portion of each of the sacrificial structures with a corresponding one of contact plugs,   wherein each of the contact plugs contacts a top surface of a corresponding one of the plurality of gate electrodes.   
     
     
       14. The method of  claim 13 , wherein
 the insulating layers include silicon oxide, and   the sacrificial layers include silicon nitride.   
     
     
       15. The method of  claim 13 , further comprising:
 forming a second insulating portion on the first insulating portion and the alternating stack; and   forming insulating layer recesses by anisotropically etching the first insulating portion and the second insulating portion,   wherein top surfaces of uppermost ones of the sacrificial layers in respective ones of the stepped surfaces are exposed through the insulating layer recesses, and   the insulating layer recesses are subsequently filled with the sacrificial structures.   
     
     
       16. The method of  claim 15 , further comprising:
 forming a spacer portion at a periphery of each of the insulating layer recesses; and   forming dummy holes by anisotropically etching through the alternating stack and a device isolation layer thereunder using a mask pattern.   
     
     
       17. The method of  claim 16 , wherein the forming the spacer portion includes:
 depositing a continuous spacer layer within the insulating layer recesses and on the second insulating portion; and   anisotropically etching the continuous spacer layer to form the spacer portion.   
     
     
       18. The method of  claim 15 , wherein the insulating layer recesses do not extend through any of the insulating layers or any of the sacrificial layers. 
     
     
       19. The method of  claim 13 , further comprising:
 forming gate dielectric layer patterns vertically passing through the alternating stack in a cell array region of the substrate,   wherein each of the gate dielectric layer patterns includes a charge storage layer and a tunneling insulating layer each running in a vertical direction.   
     
     
       20. The method of  claim 13 , wherein
 the removing the sacrificial layers includes removing the sacrificial layers via an isotropic etching process.