Multilayer interconnect structure and method for integrated circuits

Abstract

A multilayer interconnect structure is formed by, providing a substrate having thereon a first dielectric for supporting a multi-layer interconnection having lower conductor M N , upper conductor M N+1 , dielectric interlayer (DIL) and interconnecting via conductor V N+1/N . The lower conductor M N has a first upper surface located in a recess below a second upper surface of the first dielectric. The DIL is formed above the first and second surfaces. A cavity is etched through the DIL from a desired location of the upper conductor M N+1 , exposing the first surface. The cavity is filled with a further electrical conductor to form the upper conductor M N+1 and the connecting via conductor V N+1/N making electrical contact with the first upper surface. A critical dimension between others of lower conductors M N and the via conductor V N+1/N is lengthened. Leakage current and electro-migration therebetween are reduced.

What is claimed is: 
     
       1. A method for forming an integrated circuit (IC) having a multilayer interconnect structure, comprising:
 supplying a substrate having thereon an N th  dielectric, in or on which it is desired to form a multi-layer interconnection having lower conductor M N , upper conductor M N+1  and interconnecting via V N+1/N ;   forming the lower conductor M N  on the substrate with an upper surface of the lower conductor M N  recessed below an upper surface of the N th  dielectric;   providing an (N+1) th  dielectric above the N th  dielectric and the upper surface of the lower conductor M N ;   etching an (N+1) th  cavity through the (N+1) th  dielectric from a desired location of the upper conductor M N+1  and exposing the upper surface of the lower conductor M N ;   filling the (N+1) th  cavity with an electrical conductor adapted to form the upper conductor M N+1  and the connecting via V N+1/N , and make electrical contact with the upper surface of the lower conductor M N ; and   determining whether or not a desired multilevel interconnection stack having N=Q total interconnection levels is complete, and if not:   optionally removing conductor material in the (N+1) th  cavity to lower an upper surface of the upper conductor M N+1  below an upper surface of the (N+1) th  dielectric; and then   incrementing N by one and repeating providing, etching, filling, querying, and removing for any or all desired successive interconnection level N up to N=Q−1.   
     
     
       2. The method of  claim 1 , further comprising, after N=Q−1, incrementing N by one and repeating at least providing, etching, and filling for interconnection level N=Q. 
     
     
       3. The method of  claim 1 , wherein removing conductor material in the (N+1) th  cavity to lower an upper surface of the upper conductor M N+1  below an upper surface of the (N+1) th  dielectric is accomplished by chemical-mechanical-polishing (CMP). 
     
     
       4. The method of  claim 1 , wherein removing conductor material in the (N+1) th  cavity to lower an upper surface of the upper conductor M N+1  below an upper surface of the (N+1) th  dielectric is accomplished by etching an exposed surface of the upper conductor M N+1 . 
     
     
       5. The method of  claim 1 , wherein removing conductor material in the (N+1) th  cavity to lower an upper surface of the upper conductor M N+1  below an upper surface of the (N+1) th  dielectric is accomplished by converting conductive material near an exposed upper surface of the upper conductor M N+1  to an oxide of the conductive material and then removing the oxide by etching. 
     
     
       6. The method of  claim 1 , wherein forming the lower conductor M N  comprises:
 forming at least an N th  dielectric on the substrate;   etching an N th  cavity at least through the N th  dielectric, corresponding to the desired location of the lower conductor M N ;   filling the N th  cavity with electrically conductive material adapted to serve as the lower conductor M N ; and   removing conductive material in the N th  cavity to lower an upper surface of the lower conductor M N  below an upper surface of the N th  dielectric within a recess portion of the N th  dielectric around the N th  cavity.   
     
     
       7. The method of  claim 6 , wherein removing conductive material in the N th  cavity to lower an upper surface of the lower conductor M N  below an upper surface of the N th  dielectric within a recess portion of the N th  dielectric around the N th  cavity is accomplished by chemical-mechanical-polishing (CMP). 
     
     
       8. The method of  claim 1 , wherein removing conductive material in the N th  cavity to lower an upper surface of the lower conductor M N  below an upper surface of the N th  dielectric within a recess portion of the N th  dielectric around the N th  cavity is accomplished by etching an exposed surface of the upper conductor M N+1 . 
     
     
       9. The method of  claim 1 , wherein removing conductive material in the N th  cavity to lower an upper surface of the lower conductor M N  below an upper surface of the N th  dielectric within a recess portion of the N th  dielectric around the N th  cavity is accomplished by converting conductive material near an exposed upper surface of the lower conductor M N  to an oxide of the conductive material and then removing the oxide by etching. 
     
     
       10. A method for forming a multi-layer interconnection, comprising a lower conductor disposed in a first dielectric, an interlayer dielectric disposed on the first dielectric, first and second upper conductors disposed in the interlayer dielectric, and a self-aligned via conductor in electrical contact with and interconnecting the lower conductor and the first upper conductor, the method comprising:
 forming the self-aligned via conductor, the first upper conductor, and the second upper conductor comprising: 
 providing a substrate having thereon a the first dielectric for supporting the multi-layer interconnection, wherein the multi-layer interconnection has a lower conductor M N , upper conductor M N+1 , an interlayer dielectric and interconnecting via conductor V N+1/N ; and the lower conductor disposed in the first dielectric, wherein the lower conductor is elongated in a first horizontal direction and has a width in a second horizontal direction orthogonal to the first horizontal direction, and  
 wherein the lower conductor M N  has a firstan upper surface of the lower conductor is located in a recess below a secondan upper surface of the first dielectric; 
 depositing the interlayer dielectric on the first dielectric and the lower conductor;  
 forming the interlayer dielectric above the first and second surfaces; 
 etchinga cavity through the interlayer dielectric from a desired location of the upper conductor M N+1  and exposing the first surface in the recess, in desired locations of the first and second upper conductors, respective first and second upper cavities in the interlayer dielectric wherein etching a lower portion of the first upper cavity comprises selectively etching the interlayer dielectric with respect to the first dielectric and the selective etching exposes the upper surface of the lower conductor and a portion of the first dielectric; and 
 filling the cavity the first and second upper cavities with an electrical conductorto form the upper conductor M N+1  and the connecting via conductor V N+1/N  making electrical contact between a first of upper conductor M N+1  and the first upper surface in the recess; and 
 removing excess electrical conductor overlying the interlayer dielectric, thereby electrically separating the first and a second of upper conductor M N+1  an excess of electrical conductor overlying the interlayer dielectric to electrically separate the first upper conductor and the second upper conductor, 
 wherein an upper portion of the self-aligned via conductor is self-aligned to the first upper conductor and a lower portion of the self-aligned via conductor is self-aligned to the lower conductor. 
 
     
     
       11. The method of  claim 10 , further comprising, recessing an upper surfaces surface of the first upper conductor and an upper surface of the second of upper conductor M N+1  below an upper surface of the interlayer dielectric. 
     
     
       12. The method of  claim 11 , wherein the recessing comprises:
 oxidizing the upper surfaces of the first and second upper conductors; and  
 is performed by oxidation and oxide etching of the electrical conductoretching the oxidized upper surfaces. 
 
     
     
       13. The method of  claim 11 , wherein recessing the upper surfaces of the first and second upper conductors with respect to the upper surface of the interlayer dielectric comprises etching the first and second upper conductors. 
     
     
       14. The method of  claim 10 , wherein:
 the recess is elongated in the first horizontal direction; and   after forming the self-aligned via conductor, the interlayer dielectric is disposed in portions of the recess outside of the self-aligned via conductor.   
     
     
       15. The method of  claim 10 , wherein providing the lower conductor comprises:
 filling a lower cavity in the first dielectric with a conductive material;   chemical mechanical polishing excess conductive material above the lower cavity; and   subsequent to the chemical mechanical polishing, etching the conductive material.   
     
     
       16. The method of  claim 10 , wherein providing the lower conductor comprises:
 filling a lower cavity in the first dielectric with a conductive material;   chemical mechanical polishing excess conductive material above the lower cavity; and   subsequent to the chemical mechanical polishing, oxidizing the conductive material; and   etching the oxidized conductive material.   
     
     
       17. The method of  claim 10 , wherein a depth of the recess is approximately equal to a thickness of a topmost layer of the first dielectric. 
     
     
       18. The method of  claim 10 , wherein a depth of the recess is less than or equal to a thickness of a topmost layer of the first dielectric. 
     
     
       19. The method of  claim 10 , wherein a depth of the recess is between 10 nm and 100 nm. 
     
     
       20. The method of  claim 10 , wherein the lower conductor comprises copper. 
     
     
       21. The method of  claim 10 , wherein the lower conductor comprises aluminum. 
     
     
       22. The method of  claim 10 , wherein the lower conductor comprises cobalt. 
     
     
       23. The method of  claim 10 , wherein the lower conductor comprises tungsten. 
     
     
       24. The method of  claim 10 , wherein the first upper cavity is etched using two different photo-masks. 
     
     
       25. The method of  claim 10 , wherein the upper portion of the self-aligned via conductor is wider than the lower portion of the self-aligned via conductor when measured in the second horizontal direction. 
     
     
       26. The method of  claim 25 , wherein the self-aligned via conductor comprises a lateral step where the upper portion and the lower portion meet. 
     
     
       27. The method of  claim 10 , wherein a width of a self-aligned via conductor portion adjacent to an interface between the self-aligned via conductor and the lower conductor is substantially the same as a width of a lower conductor portion adjacent to the interface measured from a sidewall of the first dielectric to an opposing sidewall of the first dielectric in the second horizontal direction. 
     
     
       28. The method of  claim 10 , wherein the first and second upper conductors are elongated in the second horizontal direction. 
     
     
       29. The method of  claim 10 , wherein the first and second upper conductors are elongated in the first horizontal direction. 
     
     
       30. The method of  claim 10 , wherein:
 depositing the interlayer dielectric comprises depositing a bottommost layer of the interlayer dielectric that fills the recess.   
     
     
       31. The method of  claim 30 , wherein:
 after forming the self-aligned via conductor, the bottommost layer of the interlayer dielectric is disposed in portions of the recess outside of the self-aligned via conductor.   
     
     
       32. The method of  claim 30 , wherein the bottommost layer of the interlayer dielectric comprises a different material than a topmost layer of the interlayer dielectric. 
     
     
       33. The method of  claim 10 , wherein a topmost layer of the first dielectric comprises the same material as a topmost layer of the interlayer dielectric. 
     
     
       34. The method of  claim 33 , wherein the interlayer dielectric is sequentially formed from the same respective dielectric materials as the first dielectric. 
     
     
       35. The method of  claim 33 , wherein the topmost layer of the first dielectric and the topmost layer of the interlayer dielectric comprise silicon and nitrogen. 
     
     
       36. The method of  claim 10 , wherein a topmost layer of the first dielectric comprises silicon nitride. 
     
     
       37. The method of  claim 10 , wherein a bottommost layer of the interlayer dielectric comprises silicon carbide. 
     
     
       38. The method of  claim 10 , wherein a bottommost layer of the interlayer dielectric comprises silicon and carbon. 
     
     
       39. The method of  claim 10 , wherein a bottommost layer of the interlayer dielectric comprises silicon carbide and a topmost layer of the first dielectric comprises silicon oxide. 
     
     
       40. The method of  claim 10 , wherein a bottommost layer of the interlayer dielectric comprises silicon and carbon and a topmost layer of the first dielectric comprises silicon and oxygen. 
     
     
       41. The method of  claim 10 , wherein a bottommost layer of the interlayer dielectric comprises silicon carbide and a topmost layer of the first dielectric comprises silicon nitride. 
     
     
       42. The method of  claim 10 , wherein a bottommost layer of the interlayer dielectric comprises silicon and carbon and a topmost layer of the first dielectric comprises silicon and nitrogen. 
     
     
       43. The method of  claim 10 , wherein a bottommost layer of the interlayer dielectric comprises silicon carbide and a second dielectric layer disposed between the bottommost and a topmost layers of the interlayer dielectric comprises a low-k material. 
     
     
       44. The method of  claim 10 , wherein a bottommost layer of the interlayer dielectric comprises silicon and carbon; and
 a second dielectric layer is disposed between the bottommost and a topmost layers of the interlayer dielectric; and   the second dielectric layer comprises a low-k material.   
     
     
       45. A method for forming a multi-layer interconnection comprising a lower conductor disposed in a first dielectric, an interlayer dielectric disposed on the first dielectric, first and second upper conductors disposed in the interlayer dielectric, and a self-aligned via conductor in electrical contact with and interconnecting the lower conductor and the first upper conductor, the method comprising:
 forming the lower conductor, comprising:
 providing a substrate having the first dielectric disposed thereon; 
 etching a lower cavity in the first dielectric; 
 filling the lower cavity with a first conductive material; and 
 chemical mechanical polishing excess first conductive material overlying the first dielectric; 
 recessing an upper surface of the first conductive material from an upper surface of the first dielectric; and 
   forming the self-aligned via conductor, the first upper conductor, and the second upper conductor, comprising:
 depositing the interlayer dielectric on the first dielectric and the lower conductor; 
 etching, in desired locations of the first and second upper conductors, respective first and second upper cavities in the interlayer dielectric, wherein etching a lower portion of the first upper cavity comprises selectively etching the interlayer dielectric with respect to the first dielectric, and the selective etching exposes the upper surface of the lower conductor and a portion of the first dielectric; 
 filling the first and second upper cavities with a second conductive material; and 
 removing an excess of second conductive material overlying the interlayer dielectric to electrically separate the first upper conductor and the second upper conductor, wherein, 
 an upper portion of the self-aligned via conductor is self-aligned to the first upper conductor and a lower portion of the self-aligned via conductor is self-aligned to the lower conductor. 
   
     
     
       46. The method of  claim 45 , wherein recessing the upper surface of the first conductive material from the upper surface of the first dielectric comprises etching the conductive material. 
     
     
       47. The method of  claim 45 , wherein recessing the upper surface of the first conductive material from the first dielectric comprises oxidizing an upper portion of the conductive material and etching the oxidized upper portion of the conductive material. 
     
     
       48. The method of  claim 45 , further comprising recessing upper surfaces of the first upper conductor and the second upper conductor below an upper surface of the interlayer dielectric. 
     
     
       49. The method of  claim 48 , wherein recessing the upper surfaces of the first and second upper conductors comprises etching. 
     
     
       50. The method of  claim 48 , wherein recessing the upper surfaces of the first upper conductor and the second upper conductor comprises oxidizing upper portions of the first upper conductor and the second upper conductor and etching the oxidized upper portions. 
     
     
       51. The method of  claim 45 , wherein a recess depth of the lower conductor is approximately equal to a thickness of a topmost layer of the first dielectric. 
     
     
       52. The method of  claim 45 , wherein a recess depth of the lower conductor is between 10 nm and 100 nm. 
     
     
       53. The method of  claim 45 , wherein the lower conductor comprises copper. 
     
     
       54. The method of  claim 45 , wherein two different photo-masks are used to etch the first and second upper cavities. 
     
     
       55. A method for forming a multi-layer interconnection comprising a lower conductor disposed in a first dielectric, an interlayer dielectric disposed on the first dielectric, first and second upper conductors disposed in the interlayer dielectric, and a self-aligned via conductor in electrical contact with and interconnecting the lower conductor and the first upper conductor, the method comprising:
 forming the self-aligned via conductor, the first upper conductor, and the second upper conductor comprising:
 providing a substrate having thereon the first dielectric and the lower conductor disposed in the first dielectric, wherein the lower conductor is elongated in a first horizontal direction and has a width in a second horizontal direction orthogonal to the first horizontal direction, and 
 an upper surface of the lower conductor is located in a recess below an upper surface of the first dielectric; 
 depositing the interlayer dielectric on the first dielectric and the lower conductor; 
 etching, in desired locations of the first and second upper conductors, respective first and second upper cavities in the interlayer dielectric wherein etching a lower portion of the first upper cavity comprises selectively etching the interlayer dielectric with respect to the first dielectric and the selective etching exposes the upper surface of the lower conductor and a portion of the first dielectric; 
 filling the first and second upper cavities with an electrical conductor; and 
 removing an excess of electrical conductor overlying the interlayer dielectric to electrically separate the first upper conductor and the second upper conductor, 
   wherein an upper portion of the self-aligned via conductor is self-aligned to the first upper conductor and a lower portion of the self-aligned via conductor is self-aligned to the lower conductor; and   wherein a width of a self-aligned via conductor portion adjacent to an interface between the self-aligned via conductor and the lower conductor is substantially the same as a width of a lower conductor portion adjacent to the interface measured from a sidewall of the first dielectric to an opposing sidewall of the first dielectric in the second horizontal direction.   
     
     
       56. The method of  claim 55 , wherein:
 the recess is elongated in the first horizontal direction; and   after forming the self-aligned via conductor, the interlayer dielectric is disposed in portions of the recess outside of the self-aligned via conductor.   
     
     
       57. The method of  claim 55 , wherein providing the lower conductor comprises:
 filling a lower cavity in the first dielectric with a conductive material;   chemical mechanical polishing excess conductive material above the lower cavity; and   subsequent to the chemical mechanical polishing, etching the conductive material.   
     
     
       58. The method of  claim 55 , wherein providing the lower conductor comprises:
 filling a lower cavity in the first dielectric with a conductive material;   chemical mechanical polishing excess conductive material above the lower cavity; and   subsequent to the chemical mechanical polishing, oxidizing the conductive material; and   etching the oxidized conductive material.   
     
     
       59. The method of  claim 55 , wherein a depth of the recess is approximately equal to a thickness of a topmost layer of the first dielectric. 
     
     
       60. The method of  claim 55 , wherein a depth of the recess is less than or equal to a thickness of a topmost layer of the first dielectric. 
     
     
       61. The method of  claim 55 , wherein a depth of the recess is between 10 nm and 100 nm. 
     
     
       62. The method of  claim 55 , wherein the lower conductor comprises copper. 
     
     
       63. The method of  claim 55 , wherein the lower conductor comprises aluminum. 
     
     
       64. The method of  claim 55 , wherein the lower conductor comprises cobalt. 
     
     
       65. The method of  claim 55 , wherein the lower conductor comprises tungsten. 
     
     
       66. The method of  claim 55 , wherein the first upper cavity is etched using two different photo-masks. 
     
     
       67. The method of  claim 55 , wherein the upper portion of the self-aligned via is wider than the lower portion of the self-aligned via when measured in the second horizontal direction. 
     
     
       68. The method of  claim 67 , wherein the self-aligned via conductor comprises a lateral step where the upper portion and the lower portion meet. 
     
     
       69. The method of  claim 55 , wherein the first and second upper conductors are elongated in the second horizontal direction. 
     
     
       70. The method of  claim 55 , wherein the first and second upper conductors are elongated in the first horizontal direction. 
     
     
       71. The method of  claim 55 , wherein:
 depositing the interlayer dielectric comprises depositing a bottommost layer of the interlayer dielectric that fills the recess.   
     
     
       72. The method of  claim 71 , wherein:
 after forming the self-aligned via conductor, the bottommost layer of the interlayer dielectric is disposed in portions of the recess outside of the self-aligned via conductor.   
     
     
       73. The method of  claim 71 , wherein the bottommost layer of the interlayer dielectric comprises a different material than a topmost layer of the interlayer dielectric. 
     
     
       74. The method of  claim 55 , wherein a topmost layer of the first dielectric comprises silicon nitride. 
     
     
       75. The method of  claim 55 , wherein a bottommost layer of the interlayer dielectric comprises silicon carbide. 
     
     
       76. The method of  claim 55 , wherein a bottommost layer of the interlayer dielectric comprises silicon and carbon. 
     
     
       77. The method of  claim 55 , wherein a bottommost layer of the interlayer dielectric comprises silicon carbide and a topmost layer of the first dielectric comprises silicon oxide. 
     
     
       78. The method of  claim 55 , wherein a bottommost layer of the interlayer dielectric comprises silicon and carbon and a topmost layer of the first dielectric comprises silicon and oxygen. 
     
     
       79. The method of  claim 55 , wherein a bottommost layer of the interlayer dielectric comprises silicon carbide and a topmost layer of the first dielectric comprises silicon nitride. 
     
     
       80. The method of  claim 55 , wherein a bottommost layer of the interlayer dielectric comprises silicon and carbon and a topmost layer of the first dielectric comprises silicon and nitrogen. 
     
     
       81. The method of  claim 55 , wherein a bottommost layer of the interlayer dielectric comprises silicon carbide and a second dielectric layer disposed between the bottommost and a topmost layers of the interlayer dielectric comprises a low-k material. 
     
     
       82. The method of  claim 55 , wherein a bottommost layer of the interlayer dielectric comprises silicon and carbon; and
 a second dielectric layer is disposed between the bottommost and a topmost layers of the interlayer dielectric; and   the second dielectric layer comprises a low-k material.   
     
     
       83. A method for forming a multi-layer interconnection comprising a lower conductor disposed in a first dielectric, an interlayer dielectric disposed on the first dielectric, first and second upper conductors disposed in the interlayer dielectric, and a self-aligned via conductor in electrical contact with and interconnecting the lower conductor and the first upper conductor, the method comprising:
 forming the self-aligned via conductor, the first upper conductor, and the second upper conductor comprising:
 providing a substrate having thereon the first dielectric and the lower conductor disposed in the first dielectric, wherein the lower conductor is elongated in a first horizontal direction and has a width in a second horizontal direction orthogonal to the first horizontal direction, and 
 an upper surface of the lower conductor is located in a recess below an upper surface of the first dielectric; 
 depositing the interlayer dielectric on the first dielectric and the lower conductor; 
 etching, in desired locations of the first and second upper conductors, respective first and second upper cavities in the interlayer dielectric wherein etching a lower portion of the first upper cavity comprises selectively etching the interlayer dielectric with respect to the first dielectric and the selective etching exposes the upper surface of the lower conductor and a portion of the first dielectric; 
 filling the first and second upper cavities with an electrical conductor; and 
 removing an excess of electrical conductor overlying the interlayer dielectric to electrically separate the first upper conductor and the second upper conductor, 
   wherein the entirety of the lower conductor is disposed below the upper surface of the first dielectric; and   wherein an upper portion of the self-aligned via conductor is self-aligned to the first upper conductor and a lower portion of the self-aligned via conductor is self-aligned to the lower conductor.   
     
     
       84. The method of  claim 83 , wherein:
 the recess is elongated in the first horizontal direction; and   after forming the self-aligned via conductor, the interlayer dielectric is disposed in portions of the recess outside of the self-aligned via conductor.   
     
     
       85. The method of  claim 83 , wherein providing the lower conductor comprises:
 filling a lower cavity in the first dielectric with a conductive material;   chemical mechanical polishing excess conductive material above the lower cavity; and   subsequent to the chemical mechanical polishing, etching the conductive material.   
     
     
       86. The method of  claim 83 , wherein providing the lower conductor comprises:
 filling a lower cavity in the first dielectric with a conductive material;   chemical mechanical polishing excess conductive material above the lower cavity; and   subsequent to the chemical mechanical polishing, oxidizing the conductive material; and   etching the oxidized conductive material.   
     
     
       87. The method of  claim 83 , wherein a depth of the recess is approximately equal to a thickness of a topmost layer of the first dielectric. 
     
     
       88. The method of  claim 83 , wherein a depth of the recess is less than or equal to a thickness of a topmost layer of the first dielectric. 
     
     
       89. The method of  claim 83 , wherein a depth of the recess is between 10 nm and 100 nm. 
     
     
       90. The method of  claim 83 , wherein the lower conductor comprises copper. 
     
     
       91. The method of  claim 83 , wherein the lower conductor comprises aluminum. 
     
     
       92. The method of  claim 83 , wherein the lower conductor comprises cobalt. 
     
     
       93. The method of  claim 83 , wherein the lower conductor comprises tungsten. 
     
     
       94. The method of  claim 83 , wherein the first upper cavity is etched using two different photo-masks. 
     
     
       95. The method of  claim 83 , wherein the upper portion of the self-aligned via is wider than the lower portion of the self-aligned via when measured in the second horizontal direction. 
     
     
       96. The method of  claim 95 , wherein the self-aligned via conductor comprises a lateral step where the upper portion and the lower portion meet. 
     
     
       97. The method of  claim 83 , wherein the first and second upper conductors are elongated in the second horizontal direction. 
     
     
       98. The method of  claim 83 , wherein the first and second upper conductors are elongated in the first horizontal direction. 
     
     
       99. The method of  claim 83 , wherein:
 depositing the interlayer dielectric comprises depositing a bottommost layer of the interlayer dielectric that fills the recess.   
     
     
       100. The method of  claim 99 , wherein:
 after forming the self-aligned via conductor, the bottommost layer of the interlayer dielectric is disposed in portions of the recess outside of the self-aligned via conductor.   
     
     
       101. The method of  claim 99 , wherein the bottommost layer of the interlayer dielectric comprises a different material than a topmost layer of the interlayer dielectric. 
     
     
       102. The method of  claim 83 , wherein a topmost layer of the first dielectric comprises silicon nitride. 
     
     
       103. The method of  claim 83 , wherein a bottommost layer of the interlayer dielectric comprises silicon carbide. 
     
     
       104. The method of  claim 83 , wherein a bottommost layer of the interlayer dielectric comprises silicon and carbon. 
     
     
       105. The method of  claim 83 , wherein a bottommost layer of the interlayer dielectric comprises silicon carbide and a topmost layer of the first dielectric comprises silicon oxide. 
     
     
       106. The method of  claim 83 , wherein a bottommost layer of the interlayer dielectric comprises silicon and carbon and a topmost layer of the first dielectric comprises silicon and oxygen. 
     
     
       107. The method of  claim 83 , wherein a bottommost layer of the interlayer dielectric comprises silicon carbide and a topmost layer of the first dielectric comprises silicon nitride. 
     
     
       108. The method of  claim 83 , wherein a bottommost layer of the interlayer dielectric comprises silicon and carbon and a topmost layer of the first dielectric comprises silicon and nitrogen. 
     
     
       109. The method of  claim 83 , wherein a bottommost layer of the interlayer dielectric comprises silicon carbide and a second dielectric layer disposed between the bottommost and a topmost layers of the interlayer dielectric comprises a low-k material. 
     
     
       110. The method of  claim 83 , wherein a bottommost layer of the interlayer dielectric comprises silicon and carbon; and
 a second dielectric layer is disposed between the bottommost and a topmost layers of the interlayer dielectric; and   the second dielectric layer comprises a low-k material.   
     
     
       111. The method of  claim 83 , wherein a width of a self-aligned via conductor portion adjacent to an interface between the self-aligned via conductor and the lower conductor is substantially the same as a width of a lower conductor portion adjacent to the interface measured from a sidewall of the first dielectric to an opposing sidewall of the first dielectric in the second horizontal direction. 
     
     
       112. A method for forming a multi-layer interconnection comprising a lower conductor disposed in a first dielectric, an interlayer dielectric disposed on the first dielectric, first and second upper conductors disposed in the interlayer dielectric, and a self-aligned via conductor in electrical contact with and interconnecting the lower conductor and the first upper conductor, the method comprising:
 forming the lower conductor, comprising:
 providing a substrate having the first dielectric disposed thereon; 
 etching a lower cavity in the first dielectric; 
 filling the lower cavity with a first conductive material; and 
 chemical mechanical polishing excess first conductive material overlying the first dielectric; 
 recessing an upper surface of the first conductive material from an upper surface of the first dielectric; and 
   forming the self-aligned via conductor, the first upper conductor, and the second upper conductor, comprising:
 depositing the interlayer dielectric on the first dielectric and the lower conductor; 
 etching in desired locations of the first and second upper conductors, respective first and second upper cavities in the interlayer dielectric, wherein etching a lower portion of the first upper cavity comprises selectively etching the interlayer dielectric with respect to the first dielectric, and the selective etching exposes the upper surface of the lower conductor and a portion of the first dielectric; 
 filling the first and second upper cavities with a second conductive material; and 
 removing an excess of second conductive material overlying the interlayer dielectric to electrically separate the first upper conductor and the second upper conductor, 
 wherein, an upper portion of the self-aligned via conductor is self-aligned to the first upper conductor and a lower portion of the self-aligned via conductor is self-aligned to the lower conductor; 
 wherein a width of the self-aligned via conductor, between a first dielectric sidewall and an opposing second dielectric sidewall, and a width of the lower conductor, between the first dielectric sidewall and the opposing second dielectric sidewall, each measured at the interface therebetween and in the second horizontal direction, are substantially the same. 
   
     
     
       113. The method of  claim 112 , wherein the recessing the upper surface of the first conductive material from the upper surface of the first dielectric forms a recess elongated in the first horizontal direction; and
 after forming the self-aligned via conductor, the interlayer dielectric is disposed in portions of the recess outside of the self-aligned via conductor.   
     
     
       114. The method of  claim 112 , wherein recessing the upper surface of the first conductive material from the upper surface of the first dielectric comprises etching the conductive material. 
     
     
       115. The method of  claim 112 , wherein recessing the upper surface of the first conductive material from the first dielectric comprises oxidizing an upper portion of the conductive material and etching the oxidized upper portion of the conductive material. 
     
     
       116. The method of  claim 112 , wherein the recessing the upper surface of the first conductive material from the upper surface of the first dielectric forms a recess and a depth of the recess is approximately equal to a thickness of a topmost layer of the first dielectric. 
     
     
       117. The method of  claim 112 , wherein the recessing the upper surface of the first conductive material from the upper surface of the first dielectric forms a recess and a depth of the recess is less than or equal to a thickness of a topmost layer of the first dielectric. 
     
     
       118. The method of  claim 112 , wherein the recessing the upper surface of the first conductive material from the upper surface of the first dielectric forms a recess and a depth of the recess is between 10 nm and 100 nm. 
     
     
       119. The method of  claim 112 , wherein the lower conductor comprises copper. 
     
     
       120. The method of  claim 112 , wherein the lower conductor comprises aluminum. 
     
     
       121. The method of  claim 112 , wherein the lower conductor comprises cobalt. 
     
     
       122. The method of  claim 112 , wherein the lower conductor comprises tungsten. 
     
     
       123. The method of  claim 112 , wherein the first upper cavity is etched using two different photo-masks. 
     
     
       124. The method of  claim 112 , wherein the upper portion of the self-aligned via is wider than the lower portion of the self-aligned via when measured in the second horizontal direction. 
     
     
       125. The method of  claim 120 , wherein the self-aligned via conductor comprises a lateral step where the upper portion and the lower portion meet. 
     
     
       126. The method of  claim 112 , wherein the first and second upper conductors are elongated in the second horizontal direction. 
     
     
       127. The method of  claim 112 , wherein the first and second upper conductors are elongated in the first horizontal direction. 
     
     
       128. The method of  claim 112 , wherein:
 depositing the interlayer dielectric comprises depositing a bottommost layer of the interlayer dielectric that fills the recess.   
     
     
       129. The method of  claim 128 , wherein:
 after forming the self-aligned via conductor, the bottommost layer of the interlayer dielectric is disposed in portions of the recess outside of the self-aligned via conductor.   
     
     
       130. The method of  claim 128 , wherein the bottommost layer of the interlayer dielectric comprises a different material than a topmost layer of the interlayer dielectric. 
     
     
       131. The method of  claim 112 , wherein a topmost layer of the first dielectric comprises silicon nitride. 
     
     
       132. The method of  claim 112 , wherein a bottommost layer of the interlayer dielectric comprises silicon carbide. 
     
     
       133. The method of  claim 112 , wherein a bottommost layer of the interlayer dielectric comprises silicon and carbon. 
     
     
       134. The method of  claim 112 , wherein a bottommost layer of the interlayer dielectric comprises silicon carbide and a topmost layer of the first dielectric comprises silicon oxide. 
     
     
       135. The method of  claim 112 , wherein a bottommost layer of the interlayer dielectric comprises silicon and carbon and a topmost layer of the first dielectric comprises silicon and oxygen. 
     
     
       136. The method of  claim 112 , wherein a bottommost layer of the interlayer dielectric comprises silicon carbide and a topmost layer of the first dielectric comprises silicon nitride. 
     
     
       137. The method of  claim 112 , wherein a bottommost layer of the interlayer dielectric comprises silicon and carbon and a topmost layer of the first dielectric comprises silicon and nitrogen. 
     
     
       138. The method of  claim 112 , wherein a bottommost layer of the interlayer dielectric comprises silicon carbide and a second dielectric layer disposed between the bottommost and a topmost layers of the interlayer dielectric comprises a low-k material. 
     
     
       139. The method of  claim 112 , wherein:
 a bottommost layer of the interlayer dielectric comprises silicon and carbon; and   a second dielectric layer is disposed between the bottommost and a topmost layers of the interlayer dielectric; and   the second dielectric layer comprises a low-k material.   
     
     
       140. A method for forming a multi-layer interconnection comprising a lower conductor disposed in a first dielectric, an interlayer dielectric disposed on the first dielectric, first and second upper conductors disposed in the interlayer dielectric, and a self-aligned via conductor in electrical contact with and interconnecting the lower conductor and the first upper conductor, the method comprising:
 forming the lower conductor, comprising:
 providing a substrate having the first dielectric disposed thereon; 
 etching a lower cavity in the first dielectric; 
 filling the lower cavity with a first conductive material; and 
 chemical mechanical polishing excess first conductive material overlying the first dielectric; 
 recessing an upper surface of the first conductive material from an upper surface of the first dielectric; and 
 forming the self-aligned via conductor, the first upper conductor, and the second upper conductor, comprising: 
 depositing the interlayer dielectric on the first dielectric and the lower conductor; 
 etching, in desired locations of the first and second upper conductors, respective first and second upper cavities in the interlayer dielectric, wherein etching a lower portion of the first upper cavity comprises selectively etching the interlayer dielectric with respect to the first dielectric, and the selective etching exposes the upper surface of the lower conductor and a portion of the first dielectric; 
 filling the first and second upper cavities with a second conductive material; and 
 removing an excess of second conductive material overlying the interlayer dielectric to electrically separate the first upper conductor and the second upper conductor, 
 wherein the entirety of the lower conductor is disposed below the upper surface of the first dielectric; and 
 wherein, an upper portion of the self-aligned via conductor is self-aligned to the first upper conductor and a lower portion of the self-aligned via conductor is self-aligned to the lower conductor. 
   
     
     
       141. The method of  claim 140 , wherein the recessing the upper surface of the first conductive material from the upper surface of the first dielectric forms a recess elongated in the first horizontal direction; and
 after forming the self-aligned via conductor, the interlayer dielectric is disposed in portions of the recess outside of the self-aligned via conductor.   
     
     
       142. The method of  claim 140 , wherein recessing the upper surface of the first conductive material from the upper surface of the first dielectric comprises etching the conductive material. 
     
     
       143. The method of  claim 140 , wherein recessing the upper surface of the first conductive material from the first dielectric comprises oxidizing an upper portion of the conductive material and etching the oxidized upper portion of the conductive material. 
     
     
       144. The method of  claim 140 , wherein the recessing the upper surface of the first conductive material from the upper surface of the first dielectric forms a recess and a depth of the recess is approximately equal to a thickness of a topmost layer of the first dielectric. 
     
     
       145. The method of  claim 140 , wherein the upper surface of the first conductive material from the upper surface of the first dielectric forms a recess and a depth of the recess is less than or equal to a thickness of a topmost layer of the first dielectric. 
     
     
       146. The method of  claim 140 , wherein the upper surface of the first conductive material from the upper surface of the first dielectric forms a recess and a depth of the recess is between 10 nm and 100 nm. 
     
     
       147. The method of  claim 140 , wherein the lower conductor comprises copper. 
     
     
       148. The method of  claim 140 , wherein the lower conductor comprises aluminum. 
     
     
       149. The method of  claim 140 , wherein the lower conductor comprises cobalt. 
     
     
       150. The method of  claim 140 , wherein the lower conductor comprises tungsten. 
     
     
       151. The method of  claim 140 , wherein the first upper cavity is etched using two different photo-masks. 
     
     
       152. The method of  claim 140 , wherein the upper portion of the self-aligned via is wider than the lower portion of the self-aligned via when measured in the second horizontal direction. 
     
     
       153. The method of  claim 152 , wherein the self-aligned via conductor comprises a lateral step where the upper portion and the lower portion meet. 
     
     
       154. The method of  claim 140 , wherein the first and second upper conductors are elongated in the second horizontal direction. 
     
     
       155. The method of  claim 140 , wherein the first and second upper conductors are elongated in the first horizontal direction. 
     
     
       156. The method of  claim 140 , wherein:
 depositing the interlayer dielectric comprises depositing a bottommost layer of the interlayer dielectric that fills the recess.   
     
     
       157. The method of  claim 156 , wherein:
 after forming the self-aligned via conductor, the bottommost layer of the interlayer dielectric is disposed in portions of the recess outside of the self-aligned via conductor.   
     
     
       158. The method of  claim 156 , wherein the bottommost layer of the interlayer dielectric comprises a different material than a topmost layer of the interlayer dielectric. 
     
     
       159. The method of  claim 140 , wherein a topmost layer of the first dielectric comprises silicon nitride. 
     
     
       160. The method of  claim 140 , wherein a bottommost layer of the interlayer dielectric comprises silicon carbide. 
     
     
       161. The method of  claim 140 , wherein a bottommost layer of the interlayer dielectric comprises silicon and carbon. 
     
     
       162. The method of  claim 140 , wherein a bottommost layer of the interlayer dielectric comprises silicon carbide and a topmost layer of the first dielectric comprises silicon oxide. 
     
     
       163. The method of  claim 140 , wherein a bottommost layer of the interlayer dielectric comprises silicon and carbon and a topmost layer of the first dielectric comprises silicon and oxygen. 
     
     
       164. The method of  claim 140 , wherein a bottommost layer of the interlayer dielectric comprises silicon carbide and a topmost layer of the first dielectric comprises silicon nitride. 
     
     
       165. The method of  claim 140 , wherein a bottommost layer of the interlayer dielectric comprises silicon and carbon and a topmost layer of the first dielectric comprises silicon and nitrogen. 
     
     
       166. The method of  claim 140 , wherein a bottommost layer of the interlayer dielectric comprises silicon carbide and a second dielectric layer disposed between the bottommost and a topmost layers of the interlayer dielectric comprises a low-k material. 
     
     
       167. The method of  claim 140 , wherein a bottommost layer of the interlayer dielectric comprises silicon and carbon; and
 a second dielectric layer is disposed between the bottommost and a topmost layers of the interlayer dielectric; and   the second dielectric layer comprises a low-k material.   
     
     
       168. The method of  claim 140 , wherein a width of a self-aligned via conductor portion adjacent to an interface between the self-aligned via conductor and the lower conductor is substantially the same as a width of a lower conductor portion adjacent to the interface measured from a sidewall of the first dielectric to an opposing sidewall of the first dielectric in the second horizontal direction.