Master-slave flip flop

Abstract

A master-slave flip flop includes a master latch and a slave latch which are sequentially disposed on a substrate in a first direction. The master latch includes a first NMOS transistor and a first PMOS transistor each gated by a first clock signal. The first NMOS transistor and the first PMOS transistor share a first gate line extending in a second direction intersecting with the first direction. The slave latch includes a second NMOS transistor and a second PMOS transistor each gated by the first clock signal. The second NMOS transistor and the second NMOS transistor share a second gate line extending in the second direction. The first gate line and the second gate line are electrically connected to each other.

What is claimed is: 
     
       1. A master-slave flip flop comprising a master latch and a slave latch which are sequentially disposed on a substrate in a first direction,
 wherein the master latch includes a first NMOS transistor and a first PMOS transistor each gated by a first clock signal, and the first NMOS transistor and the first PMOS transistor share a first gate line extending in a second direction intersecting with different from the first direction, and 
 the slave latch includes a second NMOS transistor and a second PMOS transistor each gated by the first clock signal, and the second NMOS transistor and the second PMOS transistor share a second gate line extending in the second direction. 
 
     
     
       2. The master-slave flip flop of  claim 1 ,
 wherein the master latch further comprises:
 a third PMOS transistor which is gated by a second clock signal obtained by inverting the first clock signal and shares a drain region with the first PMOS transistor; and 
 a third NMOS transistor which is gated by the second clock signal and shares a drain region with the first NMOS transistor, and 
 
 the slave latch further comprises:
 a fourth PMOS transistor which is gated by the second clock signal and shares a drain region with the second PMOS transistor; and 
 a fourth NMOS transistor which is gated by the second clock signal and shares a drain region with the second NMOS transistor. 
 
 
     
     
       3. The master-slave flip flop of  claim 2 , wherein the third PMOS transistor includes a third gate line extending in the second direction, and
 the third NMOS transistor includes a fourth gate line extending in the second direction. 
 
     
     
       4. The master-slave flip flop of  claim 3 , wherein the third gate line is disposed on one side of the first gate line, and the fourth gate line is disposed on the other side of the first gate line. 
     
     
       5. The master-slave flip flop of  claim 4 , wherein the substrate has a first active region in which the first PMOS transistor is formed, and a second active region in which the first NMOS transistor is formed, and
 the third gate line does not overlap the second active region, and the fourth gate line does not overlap the first active region. 
 
     
     
       6. The master-slave flip flop of  claim 2 , wherein the fourth PMOS transistor includes a third gate line extending in the second direction, and
 the fourth NMOS transistor includes a fourth gate line extending in the second direction. 
 
     
     
       7. The master-slave flip flop of  claim 6 , wherein the third gate line and the fourth gate line are not aligned in the second direction. 
     
     
       8. The master-slave flip flop of  claim 2 , further comprising:
 an inverter, 
 wherein the first clock signal is directly input from a clock signal terminal without passing through the inverter, and 
 the inverter inverts the first clock signal to output the second dock signal. 
 
     
     
       9. The master-slave flip flop of  claim 1 , further comprising:
 a first fin and a second fin formed to protrude from the substrate and extending in the first direction, 
 wherein the first PMOS transistor is a fin-type transistor formed by intersection of the first gate line and the first fin, and 
 the first NMOS transistor is a fin-type transistor formed by intersection of the first gate line and the second fin. 
 
     
     
       10. A master-slave flip flop comprising a first master slave circuit and a second master slave circuit which share a first clock signal,
 wherein the first master slave circuit includes a first master latch and a first slave latch disposed on a substrate sequentially in a first direction, 
 the second master slave circuit includes a second master latch and a second slave latch disposed on the substrate sequentially in the first direction, 
 the first master latch includes a first NMOS transistor and a first PMOS transistor each gated by the first clock signal, and the first NMOS transistor and the first PMOS transistor share a first gate line extending in a second direction intersecting with the first direction, 
 the second master latch includes a second PMOS transistor and a second NMOS transistor which share the first gate line and are each gated by the first clock signal, 
 the first slave latch includes a third NMOS transistor and a third PMOS transistor each gated by the first clock signal, and the third NMOS transistor and the third PMOS transistor share a second gate line extending in the second direction, and 
 the second slave latch includes a fourth PMOS transistor and a fourth NMOS transistor which share the second gate line and are each gated by the first clock signal. 
 
     
     
       11. The master-slave flip flop of  claim 10 , wherein the first master latch and the second master latch are disposed side by side in the first second direction. 
     
     
       12. The master-slave flip flop of  claim 10 , Wherein the first slave latch includes a fifth NMOS transistor including a third gate line extending in the second direction on one side of the second gate line, and
 the second slave latch includes a sixth NMOS transistor sharing the third gate line, and the fifth NMOS transistor and the sixth NMOS transistor are aligned in the second direction. 
 
     
     
       13. The master-slave flip flop of  claim 10 , wherein the first master latch includes a fifth NMOS transistor including a third gate line extending in the second direction on one side of the first gate line, and
 the second master latch includes a sixth NMOS transistor sharing the third gate line, and the fifth NMOS transistor and the sixth NMOS transistor are aligned in the second direction. 
 
     
     
       14. The master-slave flip flop of  claim 13 , wherein the first master latch further includes a fifth PMOS transistor including a fourth gate line extending in the second direction on the other side of the first gate line,
 the second master latch further includes a sixth PMOS transistor including a fifth gate line extending in the second direction on the other side of the first gate line, and 
 the fourth gate line and the fifth gate line are aligned in the second direction. 
 
     
     
       15. The master-slave flip flop of  claim 14 , wherein the fourth gate line and the fifth gate line are connected to each other, and
 the fifth PMOS transistor and the sixth PMOS transistor share the fourth gate line and the fifth gate line connected to each other.   
     
     
       16. The master-slave flip flop of  claim 10 , further comprising:
 an inverter, 
 wherein the first clock signal is directly input from a clock signal terminal without passing through the inverter, and 
 the inverter inverts the first clock signal to output a second clock signal. 
 
     
     
       17. A master-slave flip flop comprising a master latch and a slave latch which are disposed side by side in a second first direction intersecting with different from a first second direction and share a first power rail and a second power rail, on a substrate including a first active region and a second active region each extending in the first direction and spaced apart from each other in the second direction,
 wherein the master latch includes:
 a first gate line extending in the second direction; 
 a first transistor formed by overlap of the first gate line and the first active region; and 
 a second transistor formed by overlap of the first gate line and the second active region, and 
 
 the slave latch includes:
 a second gate line extending in the second direction; 
 a third transistor formed by overlap of the second gate line and the first active region; and 
 a fourth transistor formed by overlap of the second gate line and the second active region. 
 
 
     
     
       18. The master-slave flip flop of  claim 17 , wherein the master latch further comprises:
 a third gate line which extends in the second direction on one side of the first gate line and overlaps the first active region to form a fifth transistor; and 
 a fourth gate line which extends in the second direction on the other side of the first gate line and overlaps the second active region to form a sixth transistor. 
 
     
     
       19. The master-slave flip flop of  claim 18 , wherein the third gate line does not overlap the second active region, and
 the fourth gate line does not overlap the first active region. 
 
     
     
       20. The master-slave flip flop of  claim 17 , wherein the slave latch comprises:
 a third gate line which extends in the second direction on one side of the second gate line and overlaps the first active region to form a fifth transistor; and 
 a fourth gate line which extends in the second direction on the other side of the first gate line and overlaps the second active region to form a sixth transistor. 
 
     
     
       21. The master-slave flip flop of  claim 3 , wherein a length of the first gate line is greater than a length of the third gate line in the second direction and is greater than a length of the fourth gate line in the second direction.  
     
     
       22. The master-slave flip flop of  claim 2 , wherein the third PMOS transistor includes a third gate line extending in the second direction.  
     
     
       23. The master-slave flip flop of  claim 2 , wherein the third NMOS transistor includes a third gate line extending in the second direction.  
     
     
       24. The master-slave fliip flop of  claim 3 , wherein a length of the second gate line is greater than a length of the third gate line in the second direction and is greater than a length of the fourth gate line in the second direction.  
     
     
       25. The master-slave flip flop of  claim 2 , wherein the fourth PMOS transistor includes a third gate line extending in the second direction.  
     
     
       26. The master-slave flip flop of  claim 2 , wherein the fourth NMOS transistor includes a third gate line extending in the second direction.  
     
     
       27. A master-slave flip flop comprising a master latch and a slave latch which are sequentially disposed on a substrate in a first direction,
 wherein the master latch includes a plurality of first transistors, and at least two of the first transistors are gated by a first clock signal and share a first gate line,   wherein an entire length of the first gate line extends in a straight line in a second direction, and the second direction is different from the first direction,   wherein the slave latch includes a plurality of second transistors, and at least two of the second transistors are gated by the first clock signal and share a second gate line,   wherein an entire length of the second gate line extends in a straight line in the second direction.    
     
     
       28. The master-slave flip flop of  claim 27 ,
 wherein the plurality of first transistors comprises:   a first NMOS transistor;   a first PMOS transistor,   wherein the first NMOS transistor and the first PMOS transistor share the first gate line;   a third PMOS transistor which is gated by a second clock signal obtained by inverting the first clock signal and shares a drain region with the first PMOS transistor; and   a third NMOS transistor which is gated by the second clock signal and shares a drain region with the first NMOS transistor, and   the plurality of second transistors comprises:   a second NMOS transistor;   a second PMOS transistor;   wherein the second NMOS transistor and the second PMOS transistor share the second gate line;   a fourth PMOS transistor which is gated by the second clock signal and shares a drain region with the second PMOS transistor; and   a fourth NMOS transistor which is gated by the second clock signal and shares a drain region with the second NMOS transistor.    
     
     
       29. The master-slave fliip flop of  claim 28 , wherein the third PMOS transistor includes a third gate line extending in the second direction; and
 the third NMOS transistor includes a fourth gate line extending in the second direction.    
     
     
       30. The master-slave flip flop of  claim 29 , wherein the third gate line is disposed on one side of the first gate line, and the fourth gate line is disposed on the other side of the first gate line.  
     
     
       31. The master-slave flip flop of  claim 30 , wherein the substrate has a first active region in which the first PMOS transistor is formed, and a second active region in which the first NMOS transistor is formed, and
 the third gate line does not overlap the second active region, and the fourth gate line does not overlap the first active region.    
     
     
       32. The master-slave flip flop of  claim 28 , wherein the fourth PMOS transistor includes a third gate line extending in the second direction, and
 the fourth NMOS transistor includes a fourth gate line extending in the second direction.    
     
     
       33. The master-slave flip flop of  claim 32 , wherein the third gate line and the fourth gate line are not aligned in the second direction.  
     
     
       34. The master-slave flip flop of  claim 28 , further comprising:
 an inverter,   wherein the first clock signal is directly input from a clock signal terminal without passing through the inverter, and   the inverter inverts the first clock signal to output the second clock signal.    
     
     
       35. The master-slave flip flop of  claim 27 , further comprising:
 a first fin and a second fin formed to protrude from the substrate and extending in the first direction,   wherein the plurality of first transistors comprises a first NMOS transistor and a first PMOS transistor, and the first NMOS transistor and the first PMOS transistor share the first gate line,   wherein the first PMOS transistor is a fin-type transistor formed by intersection of the first gate line and the first fin, and   the first NMOS transistor is a fin-type transistor formed by intersection of the first gate line and the second fin.    
     
     
       36. A master-slave flip flop comprising a master latch and a slave latch which are sequentially disposed on a substrate in a first direction,
 wherein the master latch includes a plurality of first transistors, and at least two of the first transistors are gated by a first clock signal and share a first gate line,   wherein an entire length of the first gate line extends in a straight line in a second direction, and the second direction is different from the first direction,   wherein the slave latch includes a plurality of second transistors, and at least two of the second transistors are gated by the first clock signal and share a second gate line.    
     
     
       37. The master-slave flip flop of  claim 36 ,
 wherein the pluralitV of first transistors comprises:   a first NMOS transistor;   a first PMOS transistor,   wherein the first NMOS transistor and the first PMOS transistor share the first gate line;   a third PMOS transistor which is gated by a second clock signal obtained by inverting the first clock signal and shares a drain region with the first PMOS transistor; and   a third NMOS transistor which is gated by the second clock signal and shares a drain region with the first NMOS transistor, and   the plurality of second transistors comprises:   a second NMOS transistor;   a second PMOS transistor,   wherein the second NMOS transistor and the second PMOS transistor share the second gate line;   a fourth PMOS transistor which is gated by the second clock signal and shares a drain region with the second PMOS transistor; and   a fourth NMOS transistor which is gated by the second clock signal and shares a drain region with the second NMOS transistor.    
     
     
       38. The master-slave flip flop of  claim 37 , wherein the third PMOS transistor includes a third gate line extending in the second direction; and
 the third NMOS transistor includes a fourth gate line extending in the second direction.    
     
     
       39. The master-slave flip flop of  claim 38 , wherein the third gate line is disposed on one side of the first gate line; and the fourth gate line is disposed on the other side of the first gate line.  
     
     
       40. The master-slave flip flop of  claim 39 , wherein the substrate has a first active region in which the first PMOS transistor is formed, and a second active region in which the first NMOS transistor is formed, and
 the third gate line does not overlap the second active region, and the fourth gate line does not overlap the first active region.    
     
     
       41. The master-slave flip flop of  claim 37 , wherein the fourth PMOS transistor includes a third gate line extending in the second direction, and
 the fourth NMOS transistor includes a fourth gate line extending in the second direction.    
     
     
       42. The master-slave flip flop of  claim 41 , wherein the third gate line and the fourth gate line are not aligned in the second direction.  
     
     
       43. The master-slave flip flop of  claim 37 , further comprising:
 an inverter   wherein the first clock signal is directly input from a clock signal terminal without passing through the inverter, and   the inverter inverts the first clock signal to output the second clock signal.    
     
     
       44. The master-slave flip flop of  claim 36 , further comprising:
 a first fin and a second fin formed to protrude from the substrate and extending in the first direction,   wherein the plurality of first transistors comprises a first NMOS transistor and a first PMOS transistor, and the first NMOS transistor and the first PMOS transistor share the first gate line,   wherein the first PMOS transistor is a fin-tvpe transistor formed by intersection of the first gate line and the first fin, and   the first NMOS transistor is a fin-type transistor formed by intersection of the first gate line and the second fin.    
     
     
       45. A master-slave flip flop comprising a master latch and a slave latch which are sequentiallv disposed on a substrate in a first direction,
 wherein the master latch includes a plurality of first transistors, and at least two of the first transistors are gated by a first clock signal and share a first gate line,   wherein the slave latch includes a plurality of second transistors, and at least two of the second transistors are gated by the first clock signal and share a second gate line,   wherein an entire length of the second gate line extends in a straight line in the second direction, and the second direction is different from the first direction.    
     
     
       46. The master-slave flip flop of  claim 45 , wherein the plurality of first transistors comprises:
 a first NMOS transistor;   a first PMOS transistor,   wherein the first NMOS transistor and the first PMOS transistor share the first gate line;   a third PMOS transistor which is gated by a second clock signal obtained by inverting the first clock signal and shares a drain region with the first PMOS transistor; and   a third NMOS transistor which is gated by the second clock signal and shares a drain region with the first NMOS transistor, and   the plurality of second transistors comprises:   a second NMOS transistor;   a second PMOS transistor,   wherein the second NMOS transistor and the second PMOS transistor share the second gate line,   a fourth PMOS transistor which is gated by the second clock signal and shares a drain region with the second PMOS transistor; and   a fourth NMOS transistor which is gated by the second clock signal and shares a drain region with the second NMOS transistor.    
     
     
       47. The master-slave flip flop of  claim 46 , wherein the third PMOS transistor includes a third gate line extending in the second direction, and
 the third NMOS transistor includes a fourth gate line extending in the second direction.    
     
     
       48. The master-slave flip flop of  claim 47 , wherein the third gate line is disposed on one side of the first gate line, and the fourth gate line is disposed on the other side of the first gate line.  
     
     
       49. The master-slave flip flop of  claim 48 , wherein the substrate has a first active region in which the first PMOS transistor is formed, and a second active region in which the first NMOS transistor is formed, and
 the third gate line does not overlap the second active region, and the fourth gate line does not overlap the first active region.    
     
     
       50. The master-slave flip flop of  claim 46 , wherein the fourth PMOS transistor includes a third gate line extending in the second direction, and
 the fourth NMOS transistor includes a fourth gate line extending in the second direction.    
     
     
       51. The master-slave flip flop of  claim 50 , wherein the third gate line and the fourth gate line are not aligned in the second direction.  
     
     
       52. The master-slave flip flop of  claim 46 , further comprising:
 an inverter   wherein the first clock signal is directly input from a clock signal terminal without passing through the inverter, and   the inverter inverts the first clock signal to output the second clock signal.    
     
     
       53. The master-slave flip flop of  claim 45 , further comprising: 
       a first fin and a second fin formed to protrude from the substrate and extending in the first direction,
 wherein the plurality of first transistors comprises a first NMOS transistor and a first PMOS transistor, and the first NMOS transistor and the first PMOS transistor share the first gate line, 
 wherein the first PMOS transistor is a fin-type transistor formed by intersection of the first gate line and the first fin, and 
 the first NMOS transistor is a fin-type transistor formed by intersection of the first gate line and the second fin.  
 
     
     
       54. A master-slave flip flop comprising a master circuit and a slave circuit which are sequentiallv disposed on a substrate in a first direction, the master-slave flip flop comprising:
 the master circuit comprising a plurality of first transistors, wherein at least two of the first transistors are gated by a first clock signal and share a first gate line straightly extending in a second direction intersecting the first direction;   the slave circuit comprising a plurality of second transistors, wherein at least two of the second transistors are gated by the first clock signal and share a second gate line straightly extending in the second direction; and   an inverter   wherein the first clock signal is directly provided from a clock signal terminal without passing through the inverter and gates the at least two of the first transistors and the at least two of the second transistors, and   a second clock signal is an inversion of the first clock signal provided by the inverter, and the second clock signal gates other transistors of the first transistors and other transistors of the second transistors.    
     
     
       55. A master-slave flip flop comprising a master latch and a slave latch which are sequentially disposed on a substrate in a first direction,
 wherein the master latch includes a first NMOS transistor and a first PMOS transistor each gated by a first clock signal, and the first NMOS transistor and the first PMOS transistor share a first gate line extending in a second direction different from the first direction,   the slave latch includes a second NMOS transistor and a second PMOS transistor each gated by the first clock signal, and the second NMOS transistor and the second PMOS transistor share a second gate line extending in the second direction, and   the first clock signal is directly applied to the master latch from a clock signal terminal.    
     
     
       56. An integrated circuit comprising a master latch and a slave latch which are sequentially disposed on a substrate in a first direction, the integrated circuit comprising:
 a scan circuit connected to the master latch,   wherein the master latch operates under control of the scan circuit;   the master latch,   wherein the master latch comprises a plurality of first transistors, and at least two of the first transistors are gated by a first clock signal and share a first gate line straightly extending in a second direction different from the first direction; and   the slave latch,   wherein the slave latch comprises a plurality of second transistors,   wherein at least two of the second transistors are gated by the first clock signal and share a second gate line straightly extending in the second direction.   
     
     
       57. The integrated circuit of  claim 56 , wherein the scan circuit comprises:
 a first scan tri-state inverter that receives a scan input signal;   an inverter that receives a scan enable signal; and   a second scan tri-state inverter that receives a data signal,   wherein the scan circuit outputs the scan input signal to the master latch through the first scan tri-state inverter, and outputs the data signal to the master latch through the second scan tri-state inverter, based on the scan enable signal.    
     
     
       58. A master-slave flip flop comprising a master latch and a slave latch which are sequentiallv disposed on a substrate in a first direction,
 wherein the master latch includes a plurality of first transistors, and the slave latch includes a plurality of second transistors,   wherein a first first transistor of the plurality of first transistors is connected to a first gate line extending in a second direction different from the first direction, a second first transistor of the plurality of first transistors is connected to a second gate line extending in the second direction, and a third first transistor of the plurality of first transistors is connected to a third gate line extending in the second direction,   wherein the first first transistor is gated by a first clock signal, and each of the second first transistor and the third first transistor is gated by a second clock signal obtained by inverting the first clock signal,   wherein each transistor among the plurality of second transistors is gated by the first clock signal or the second clock signal,   wherein the first gate line is disposed in a first column extending in the second direction, the second gate line is disposed in a second column extending in the second direction, and the third gate line is disposed in a third column extending in the second direction,   wherein the first, second and third columns are spaced apart from on another in the first direction.    
     
     
       59. The master-slave flip flop of  claim 58 , wherein no intervening gate lines are disposed between the first gate line and the second gate line, and no intervening gate lines are disposed between the first gate line and the third gate line.  
     
     
       60. The master-slave flip flop of  claim 58 , wherein a first second transistor of the plurality of second transistors is connected to a fourth gate line extending in the second direction, a second second transistor of the plurality of second transistors is connected to a fifth gate line extending in the second direction, and a third second transistor of the plurality of second transistors is connected to a sixth gate line extending in the second direction,
 wherein the fourth gate line is disposed in a fourth column extending in the second direction, the fifth gate line is disposed in a fifth column extending in the second direction, and the sixth gate line is disposed in a sixth column extending in the second direction,   wherein the fourth column, the fifth column and the sixth column are spaced apart from one another in the first direction.    
     
     
       61. The master-slave flip flop of  claim 60 , wherein no intervening gate lines are disposed between the fourth gate line and the fifth gate line, and no intervening gate lines are disposed between the fourth gate line and the sixth gate line.  
     
     
       62. The master-slave flip flop of  claim 60 ,
 wherein the first first transistor is an NMOS transistor, the second first transistor is an NMOS transistor, and the third first transistor is a PMOS transistor,   wherein the plurality of first transistors further comprises a fourth first transistor which is a PMOS transistor,   wherein the first first transistor and the fourth first transistor share the first gate line, and the fourth first transistor is gated by the first clock signal,   wherein the third first transistor is gated by the second clock signal obtained by inverting the first clock signal and shares a drain region with the fourth first transistor,   wherein the second first transistor shares a drain region with the first first transistor.    
     
     
       63. The master-slave flip flop of  claim 62 ,
 wherein the first second transistor is an NMOS transistor, the second second transistor is a PMOS transistor, and the third second transistor is an NMOS transistor,   wherein the plurality of second transistors further comprises a fourth second transistor which is a PMOS transistor,   wherein the first second transistor and the fourth second transistor are gated by the first clock signal and share the fourth gate line,   wherein the third second transistor is gated by the second clock signal obtained by inverting the first clock signal and shares a drain region with the first second transistor,   wherein the second second transistor is gated by the second clock signal and shares a drain region with the fourth second transistor.    
     
     
       64. The master-slave flip flop of  claim 58 , wherein the second gate line is disposed on one side of the first gate line, and the third gate line is disposed on the other side of the first gate line.  
     
     
       65. The master-slave flip flop of  claim 60 , wherein the fifth gate line is disposed on one side of the fourth gate line, and the sixth gate line is disposed on the other side of the fourth gate line.  
     
     
       66. A master-slave flip flop comprising a master latch and a slave latch which are sequentially disposed on a substrate in a first direction,
 wherein the slave latch includes a plurality of first transistors, and the master latch includes a plurality of second transistors,   wherein a first first transistor of the plurality of first transistors is connected to a first gate line extending in a second direction different from the first direction, a second first transistor of the plurality of first transistors is connected to a second gate line extending in the second direction, and a third first transistor of the plurality of first transistors is connected to a third gate line extending in the second direction,   wherein the first first transistor is gated by a first clock signal, and each of the second first transistor and the third first transistor is gated by a second clock signal obtained by inverting the first clock signal,   wherein each transistor among the plurality of second transistors is gated by the first clock signal or the second clock signal,   wherein the first gate line is disposed in a first column extending in the second direction, the second gate line is disposed in a second column extending in the second direction, and the third gate line is disposed in a third column extending in the second direction,   wherein the first column, the second column and the third column are spaced apart from one another in the first direction.    
     
     
       67. The master-slave flip flop of  claim 66 , wherein no intervening gate lines are disposed between the first gate line and the second gate line, and no intervening gate lines are disposed between the first gate line and the third gate line.  
     
     
       68. A master-slave flip flop comprising a master latch and a slave latch which are disposed side by side in a first direction different from a second direction, the master-slave flip flop comprising:
 a first power rail; and   a second power rail,   wherein the master latch and the slave latch share the first power rail and the second power rail,   wherein the master latch and the slave latch are disposed on a substrate including a first active region and a second active region each extending in the first direction and spaced apart from each other in the second direction,   wherein the master latch includes:   a first gate line straightly extending in the second direction;   a first transistor formed by overlap of the first gate line and the first active region; and   a second transistor formed by overlap of the first gate line and the second active region, wherein a first clock signal is provided to the first gate line, and   the slave latch includes:   a second gate line straightly extending in the second direction;   a third transistor formed by overlap of the second gate line and the first active region; and   a fourth transistor formed by overlap of the second gate line and the second active region, wherein the first clock signal is provided to the second gate line.    
     
     
       69. The master-slave flip flop of  claim 68 , wherein the first power rail is adjacent to the second power rail.  
     
     
       70. The master-slave flip flop of  claim 68 , wherein no intervening power rails are disposed between the first power rail and the second power rail.  
     
     
       71. A master-slave flip flop comprising a master latch and a slave latch which are sequentially disposed on a substrate in a first direction, the master-slave flip flop comprising:
 a first power rail extending in the first direction that transmits a first voltage; and   a second power rail extending in the first direction that transmits a second voltage,   wherein the master latch includes a plurality of first transistors connected between the first power rail and the second power rail, and at least two of the first transistors are gated by a first clock signal and share a first gate line,   wherein an entire length of the first gate line extends in a straight line in a second direction, and the second direction is different from the first direction,   wherein the slave latch includes a plurality of second transistors connected between the first power rail and the second power rail; and at least two of the second transistors are gated by the first clock signal and share a second gate line,   wherein the master latch and the slave latch share the first power rail and the second power rail.    
     
     
       72. The master-slave flip flop of  claim 71 ,
 wherein the plurality of first transistors comprises:   a first NMOS transistor;   a first PMOS transistor,   wherein the first NMOS transistor and the first PMOS transistor share the first gate line;   a third PMOS transistor which is gated by a second clock signal obtained by inverting the first clock signal and shares a drain region with the first PMOS transistor; and   a third NMOS transistor which is gated by the second clock signal and shares a drain region with the first NMOS transistor, and   the plurality of second transistors comprises:   a second NMOS transistor;   a second PMOS transistor;   wherein the second NMOS transistor and the second PMOS transistor share the second gate line;   a fourth PMOS transistor which is gated by the second clock signal and shares a drain region with the second PMOS transistor; and   a fourth NMOS transistor which is gated by the second clock signal and shares a drain region with the second NMOS transistor.    
     
     
       73. A master-slave flip flop comprising a master latch and a slave latch which are sequentially disposed on a substrate in a first direction, the master-slave flip flop comprising:
 a first power rail extending in the first direction that transmits a first voltage; and   a second power rail extending in the first direction that transmits a second voltage,   wherein the master latch includes a plurality of first transistors connected between the first power rail and the second power rail, and at least two of the first transistors are gated by a first clock signal and share a first gate line,   wherein the slave latch includes a plurality of second transistors connected between the first power rail and the second power rail, and at least two of the second transistors are gated by the first clock signal and share a second gate line,   wherein an entire length of the second gate line extends in a straight line in a second direction, and the second direction is different from the first direction,   wherein the master latch and the slave latch share the first power rail and the second power rail.    
     
     
       74. The master-slave flip flop of  claim 73 ,
 wherein the plurality of first transistors comprises:   a first NMOS transistor;   a first PMOS transistor,   wherein the first NMOS transistor and the first PMOS transistor share the first gate line;   a third PMOS transistor which is gated by a second clock signal obtained by inverting the first clock signal and shares a drain region with the first PMOS transistor; and   a third NMOS transistor which is gated by the second clock signal and shares a drain region with the first NMOS transistor, and   the plurality of second transistors comprises:   a second NMOS transistor;   a second PMOS transistor;   wherein the second NMOS transistor and the second PMOS transistor share the second gate line;   a fourth PMOS transistor which is gated by the second clock signal and shares a drain region with the second PMOS transistor; and   a fourth NMOS transistor which is gated by the second clock signal and shares a drain region with the second NMOS transistor.    
     
     
       75. A master-slave flip flop comprising a master latch and a slave latch which are sequentially disposed on a substrate in a first direction, the master-slave flip flop comprising:
 a first power rail extending in the first direction that transmits a first voltage; and   a second power rail extending in the first direction that transmits a second voltage,   wherein the master latch includes a first NMOS transistor and a first PMOS transistor each gated by a first clock signal and connected between the first power rail and the second power rail, and the first NMOS transistor and the first PMOS transistor share a first gate line extending in a second direction different from the first direction,   the slave latch includes a second NMOS transistor and a second PMOS transistor each gated by the first clock signal and connected between the first power rail and the second power rail, and the second NMOS transistor and the second PMOS transistor share a second gate line extending in the second direction,   the first clock signal is directly applied to the master latch from a clock signal terminal, and   the master latch and the slave latch share the first power rail and the second power rail.    
     
     
       76. A master-slave flip flop comprising a master latch and a slave latch which are disposed side by side in a first direction different from a second direction, the master-slave flip flop comprising:
 a first power rail;   a second power rail,   wherein the master latch and the slave latch share the first power rail and the second power rail,   wherein the master latch and the slave latch are disposed on a substrate including a first active region and a second active region each extending in the first direction and spaced apart from each other in the second direction,   wherein the master latch comprises:   a first gate line extending in the second direction;   wherein an entire length of the first gate line extends in a straight line in the second direction;   a first transistor formed by overlap of the first gate line and the first active region; and   a second transistor formed by overlap of the first gate line and the second active region; and   wherein the slave latch comprises:   a second gate line extending in the second direction;   wherein an entire length of the second gate line extends in a straight line in the second direction;   a third transistor formed by overlap of the second gate line and the first active region; and   a fourth transistor formed by overlap of the second gate line and the second active region.    
     
     
       77. The master-slave flip flop of  claim 76 , wherein the master latch further comprises:
 a third gate line which extends in the second direction on one side of the first gate line and overlaps the first active region to form a fifth transistor; and   a fourth gate line which extends in the second direction on the other side of the first gate line and overlaps the second active region to form a sixth transistor.    
     
     
       78. The master-slave flip flop of  claim 77 , wherein the third gate line does not overlap the second active region, and 
       the fourth gate line does not overlap the first active region.  
     
     
       79. The master-slave flip flop of  claim 76 , wherein the slave latch further comprises:
 a third gate line which extends in the second direction on one side of the second gate line and overlaps the first active region to form a fifth transistor; and   a fourth gate line which extends in the second direction on the other side of the first gate line and overlaps the second active region to form a sixth transistor.