Non-volatile semiconductor storage device

Abstract

A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.

What is claimed is: 
     
       1. A non-volatile semiconductor storage device comprising:
 a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and   a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells;   each of the plurality of transfer transistors comprising:   a gate electrode formed on a semiconductor substrate via a gate insulation film;   diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers; and   upper layer wirings provided above the diffusion layers, wherein   the transfer transistors comprise enhancement-type transistors and depression-type transistors,   the upper layer wirings provided above the transfer transistors corresponding to the enhancement-type transistors are provided with a predetermined voltage at least when the transfer transistors become conductive to prevent depletion of the diffusion layer, and   the upper layer wirings provided above the transfer transistors corresponding to the depression-type transistors are supplied with a fixed voltage smaller than a voltage applied to their gates.   
     
     
       2. The non-volatile semiconductor storage device according to  claim 1 , further comprising:
 a row decoder selecting a word line provided above the memory cell array,   wherein the transfer transistors are included in the row decoder.   
     
     
       3. The non-volatile semiconductor storage device according to  claim 1 , wherein
 the upper layer wirings of the transfer transistors corresponding to the enhancement-type transistors are provided with the same voltage as that of the gate electrode.   
     
     
       4. The non-volatile semiconductor storage device according to  claim 3 , wherein
 the upper layer wirings of the transfer transistors corresponding to the enhancement-type transistors are short-circuited to the gate electrode.   
     
     
       5. The non-volatile semiconductor storage device according to  claim 1 , wherein
 the upper layer wirings of the transfer transistors corresponding to the enhancement-type transistors are provided with the same voltage as that of the diffusion layers.   
     
     
       6. The non-volatile semiconductor storage device according to  claim 5 , wherein
 the upper layer wirings of the transfer transistors corresponding to the enhancement-type transistors are short-circuited to the diffusion layers.   
     
     
       7. The non-volatile semiconductor storage device according to  claim 1 , further comprising:
 a short-circuit wiring short-circuiting the upper layer wirings to the gate electrode.   
     
     
       8. The non-volatile semiconductor storage device according to  claim 1 , wherein
 the memory cell array comprises NAND cells including a plurality of serially-connected memory cells, and selection transistors connected to the NAND cells.   
     
     
       9. The non-volatile semiconductor storage device according to  claim 1 , wherein
 each of the diffusion layers comprises a high concentration area with a first impurity concentration and an LDD area with a second impurity concentration lower than the first impurity concentration.   
     
     
       10. The non-volatile semiconductor storage device according to  claim 9 , wherein
 the upper layer wirings are provided above the LDD areas.   
     
     
       11. The non-volatile semiconductor storage device according to  claim 1 , wherein
 the plurality of transfer transistors share the gate electrode as well as the upper layer wirings that are disposed in a continuous manner.   
     
     
       12. The non-volatile semiconductor storage device according to  claim 1 , wherein
 the plurality of transfer transistors share the gate electrode, and   the upper layer wirings are separately disposed for one or two of the plurality of transfer transistors.   
     
     
       13. The non-volatile semiconductor storage device according to  claim 1 , further comprising:
 a signal line electrically connected to the diffusion layers, wherein the upper layer wirings are short-circuited to the signal line.   
     
     
       14. A non-volatile semiconductor storage device comprising:
 a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and   a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells;   each of the plurality of transfer transistors comprising:   a gate electrode formed on a semiconductor substrate via a gate insulation film;   diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers; and   upper layer wirings provided above the diffusion layers,   wherein   the transfer transistors comprise enhancement-type transistors and depression-type transistors,   the upper layer wirings provided above the transfer transistors corresponding to the enhancement-type transistors are provided with the same voltage as applied to the diffusion layers or the gate voltage at least when the transfer transistors become conductive, and   the upper layer wirings provided above the transfer transistors corresponding to the depression-type transistors are supplied with a fixed voltage smaller than a voltage applied to their gates.   
     
     
       15. The non-volatile semiconductor storage device according to  claim 14 , further comprising:
 a row decoder selecting a word line provided above the memory cell array,   wherein the transfer transistors are included in the row decoder.   
     
     
       16. The non-volatile semiconductor storage device according to  claim 14 , wherein
 the upper layer wirings of the transfer transistors corresponding to the enhancement-type transistors are short-circuited to the gate electrode.   
     
     
       17. The non-volatile semiconductor storage device according to  claim 14 , wherein
 the upper layer wirings of the transfer transistors corresponding to the enhancement-type transistors are short-circuited to the diffusion layers.   
     
     
       18. A non-volatile semiconductor storage device comprising:
 a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and   a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells;   each of the plurality of transfer transistors comprising:   a gate electrode formed on a semiconductor substrate via a gate insulation film;   diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers; and   upper layer wirings provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive,   wherein the plurality of transfer transistors share the gate electrode, and   the upper layer wirings are separately disposed for one or two of the plurality of transfer transistors.   
     
     
       19. A non-volatile semiconductor storage device comprising:
 a memory cell array including a plurality of memory cells;   a plurality of transfer transistors configured to transfer a voltage to the memory cells, the transfer transistors including:   a first transfer transistor, and   a second transfer transistor,
 the first and second transfer transistors comprising a common gate electrode extending in a first direction, 
 the first transfer transistor comprising a first active region and a second active region arranged in a second direction with the common gate electrode as a center, the second direction crossing the first direction, 
 the second transfer transistor comprising a third active region and a fourth active region arranged in the second direction with the common gate electrode as a center; and 
   a first wiring electrically connected to the first active region, the first wiring comprising
 a first portion extending in the first direction, the first portion at least partially overlapping with the first active region when viewed in a third direction, the third direction crossing the first direction and the second direction, 
 a second portion extending in the first direction between the first portion and the common gate electrode in the second direction, the second portion at least partially overlapping with the first active region when viewed in the third direction, and 
 a third portion extending in the second direction to electrically connect the first and second portions.  
   
     
     
       20. The non-volatile semiconductor storage device according to  claim 19 , further comprising:
 a first contact extending in the third direction to connect the first portion of the first wiring and the first active region,   wherein no contact is connected to the second portion and to the third portion.    
     
     
       21. The non-volatile semiconductor storage device according to  claim 19 , further comprising:
 a substrate in which the first transistor and the second transistor are formed, wherein   a distance between the substrate and the common gate electrode of the first transistor and the second transistor in the third direction is smaller than a distance between the substrate and the first wiring in the third direction.    
     
     
       22. The non-volatile semiconductor storage device according to  claim 21 , further comprising:
 a second wiring electrically connected to the second active region;   a third wiring electrically connected to the third active region;   a fourth wiring electrically connected to the fourth active region; and   a voltage generation circuit configured to supply voltages to the second wiring and the fourth wiring, respectively.    
     
     
       23. The non-volatile semiconductor storage device according to  claim 22 , wherein
 the first wiring is electrically connected to one of gates of the memory cells, and   the third wiring is electrically connected to another one of the gates of the memory cells.    
     
     
       24. The non-volatile semiconductor storage device according to  claim 23 , wherein
 the distance between the substrate and the common gate electrode of the first transistor and the second transistor in the third direction is smaller than a distance between the substrate and the third wiring in the third direction.    
     
     
       25. The non-volatile semiconductor storage device according to  claim 24 , wherein
 the distance between the substrate and the common gate electrode of the first transistor and the second transistor in the third direction is smaller than a distance between the substrate and the second wiring in the third direction and a distance between the substrate and the fourth wiring in the third direction.    
     
     
       26. The non-volatile semiconductor storage device according to  claim 24 , wherein
 the second wiring comprises a fourth portion extending in the second direction.    
     
     
       27. The non-volatile semiconductor storage device according to  claim 26 , wherein
 the second wiring further comprises:
 a fifth portion extending in the first direction, the fifth portion at least partially overlapping with the second active region when viewed in the third direction; 
 a second contact extending in the third direction to connect the fourth portion and the fifth portion; and 
 a third contact extending in the third direction to connect the fifth portion first and the second active region.  
   
     
     
       28. The non-volatile semiconductor storage device according to  claim 27 , wherein
 a distance between the substrate and the fourth portion of the second wiring in the third direction is larger than a distance between the substrate and the fifth portion of the second wiring in the third direction.    
     
     
       29. The non-volatile semiconductor storage device according to  claim 19 , further comprising:
 a row decoder in which the first and second transfer transistors are included.    
     
     
       30. The non-volatile semiconductor storage device according to  claim 19 , wherein
 the memory cell array comprises NAND cells including the memory cells connected in series, a first selection transistor connected to one end of the serially-connected memory cells and a second selection transistor connected to the other end of the serially-connected memory cells.    
     
     
       31. The non-volatile semiconductor storage device according to  claim 30 . wherein
 each of the memory cells includes a charge storage portion.