Semiconductor devices having a gate isolation layer and methods of manufacturing the same

Abstract

Semiconductor devices are provided. A semiconductor device includes a channel region that protrudes from a substrate. The semiconductor device includes a gate line on the channel region. Moreover, the semiconductor device includes a gate isolation layer that is between a first portion of the gate line and a second portion of the gate line. The gate isolation layer is in contact with the gate line and includes a gap that is in the gate isolation layer. Related methods of manufacturing a semiconductor device are also provided.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a first channel region and a second channel region that protrude from a substrate and that extend in a first direction;   a first gate on the first channel region;   a second gate on the second channel region, wherein the first gate and the second gate extend in a second direction intersecting the first direction and are spaced apart from each other in the second direction;   a first gate insulating layer between the first gate and the first channel region;   a second gate insulating layer between the second gate and the second channel region; and   a gate isolation layer between the first gate and the second gate,   wherein the gate isolation layer is in contact with the first gate and the second gate and comprises a gap that is in the gate isolation layer,   wherein a first width of the gate isolation layer in the second direction is greater than a second width of the gate isolation layer in the second direction,   wherein a third width of the gate isolation layer in the second direction is less than the first width of the gate isolation layer,   wherein the first width is located between the second width and the third width in a vertical direction,   wherein the second width is at a level that is coplanar with an upper surface of the first gate, and   wherein the gate isolation layer monotonically decreases in width from the first width to the second width.   
     
     
         2 . The semiconductor device of  claim 1 ,
 wherein the first gate insulating layer and the second gate insulating layer are spaced apart from each other with the gate isolation layer therebetween, and   wherein the gate isolation layer is in contact with the first gate and the second gate at each of the first width, the second width, and the third width.   
     
     
         3 . The semiconductor device of  claim 1 , wherein a top end of the gap is at a higher level than a top end of the first channel region. 
     
     
         4 . The semiconductor device of  claim 1 ,
 wherein the first gate insulating layer is on a first side surface and a second side surface of the first gate, and   wherein the second gate insulating layer is on a first side surface and a second side surface of the second gate.   
     
     
         5 . The semiconductor device of  claim 1 , further comprising a device isolation layer that is in a trench between the first channel region and the second channel region,
 wherein the first gate insulating layer is between the first gate and the device isolation layer,   wherein the second gate insulating layer is between the second gate and the device isolation layer,   wherein an upper portion of the device isolation layer comprises a recess,   wherein a portion of the gate isolation layer is in the recess, and   wherein a bottom end of the gate isolation layer is at a lower level than a top end of the device isolation layer.   
     
     
         6 . The semiconductor device of  claim 5 , wherein a bottom end of the gap is at a lower level than the top end of the device isolation layer. 
     
     
         7 . The semiconductor device of  claim 1 ,
 wherein the gap comprises an air gap that has an elliptical shape, and   wherein a middle portion of the air gap is wider in the second direction than upper and lower portions of the air gap.   
     
     
         8 . The semiconductor device of  claim 1 , wherein, when viewed in a vertical cross-section, a sidewall of the gate isolation layer comprises a plurality of bulges. 
     
     
         9 . The semiconductor device of  claim 1 , further comprising a first capping layer and a second capping layer on the first gate and the second gate, respectively, the first capping layer and the second capping layer being spaced apart from each other in the second direction with the gate isolation layer therebetween,
 wherein a width between respective bottom ends of the first capping layer and the second capping layer is greater than a width between respective top ends of the first capping layer and the second capping layer, and a top end of the gap is at a higher level than the bottom end of the first capping layer and the bottom end of the second capping layer.   
     
     
         10 . A semiconductor device comprising:
 a substrate comprising a channel region that protrudes from the substrate;   a gate line on a first side surface and a second side surface of the channel region;   gate spacers on a first side surface and a second side surface of the gate line; and   a gate isolation layer in a gate cut region that separates a first portion of the gate line from a second portion of the gate line,   wherein the gate isolation layer is in contact with the gate line and comprises a gap that is in the gate isolation layer,   wherein a first width of the gap is greater than a second width of the gap,   wherein a third width of the gap is narrower than the first width,   wherein the first width is located between the second width and the third width,   wherein a first distance between the first and second portions of the gate line at a middle portion of the gate isolation layer is greater than a second distance between the first and second portions of the gate line adjacent a top end of the gate isolation layer,   wherein the gate line comprises one among a plurality of gate lines spaced apart from each other in a first direction that intersects a second direction in which the first portion of the gate line is separated from the second portion of the gate line,   wherein the gate cut region extends in the first direction into at least two of the plurality of gate lines,   wherein the gate isolation layer extends in the first direction in the gate cut region,   wherein the gap is at an intersection between the gate isolation layer and the gate line, and   wherein a portion of the gate cut region that is between the at least two of the plurality of gate lines increases in width toward a middle of the portion of the gate cut region.   
     
     
         11 . The semiconductor device of  claim 10 , wherein the gate cut region separates the gate spacers. 
     
     
         12 . The semiconductor device of  claim 10 , wherein the gate cut region has an elliptical shape. 
     
     
         13 . The semiconductor device of  claim 10 , further comprising a gate insulating layer between the gate line and the gate spacers. 
     
     
         14 . The semiconductor device of  claim 10 , wherein a first width of the gate cut region in the gate line is greater than a second width of the gate cut region between the at least two of the plurality of gate lines. 
     
     
         15 . The semiconductor device of  claim 10 ,
 wherein a top end of the gap is at a higher level than a top end of the channel region, and   wherein the gap extends a majority of a height of the gate cut region.   
     
     
         16 . The semiconductor device of  claim 10 ,
 wherein the gap comprises an air gap that has an elliptical shape, and   wherein a middle portion of the air gap is wider than upper and lower portions of the air gap.   
     
     
         17 . A semiconductor device comprising:
 a substrate comprising a channel region that protrudes from the substrate and that extends in a first direction;   a first gate line and a second gate line that are on the channel region and that extend in a second direction intersecting the first direction, wherein the first gate line is spaced apart from the second gate line in the first direction;   gate spacers on a first side surface and a second side surface of the first gate line;   a gate insulating layer between the first gate line and the gate spacers;   a gate isolation layer in a gate cut region that is between the first gate line and the second gate line in the first direction; and   a gap in the gate isolation layer, wherein the gate cut region separates the first gate line, separates the gate insulating layer, and separates the gate spacers,   wherein the gate isolation layer is in contact with the first gate line,   wherein a first width of the gate isolation layer is greater than, and located between in a vertical third direction, a second width and a third width of the gate isolation layer, and   wherein the first width is halfway between, in the vertical third direction, a level of an upper surface of the first gate line and a level of a lower surface of the first gate line.   
     
     
         18 . The semiconductor device of  claim 17 , wherein the gap comprises an air gap that has an elliptical shape having a minor axis in the second direction. 
     
     
         19 . The semiconductor device of  claim 1 , wherein the first width is at a level that is adjacent an upper surface of the first channel region. 
     
     
         20 . The semiconductor device of  claim 10 , wherein the first width is at a level that is adjacent an upper surface of the channel region. 
     
     
       21. A semiconductor device comprising:
 a substrate;   a plurality of channel patterns disposed on the substrate, and including a first channel pattern and a second channel pattern;   a first gate disposed on the first channel pattern, and extending in a first direction that is a horizontal direction;   a second gate disposed on the first channel pattern, and extending in the first direction;   a third gate disposed on the second channel pattern, extending in the first direction, and spaced apart from the first gate;   a fourth gate disposed on the second channel pattern, extending in the first direction, and spaced apart from the second gate;   a first insulating layer disposed between the first gate and the second gate;   a second insulating layer disposed between the third gate and the fourth gate;   a gate isolation disposed between the first gate and the third gate, between the first insulating layer and the second insulating layer, and between the second gate and the fourth gate;   a first gap disposed in the gate isolation, and disposed between the first gate and the third gate; and   a second gap disposed in the gate isolation, and disposed between the first insulating layer and the second insulating layer,   wherein the gate isolation includes a first portion disposed between the first gate and the third gate, a second portion disposed between the first insulating layer and the second insulating layer, and a third portion disposed between the first portion and the second portion,   the first portion of the gate isolation includes a first part and a second part disposed lower than the first part in a second direction that is a vertical direction,   a first width of the first part of the first portion of the gate isolation is different from a second width of the second part of the first portion of the gate isolation, each of the first width and the second width being in the first direction,   the first width is halfway between, in the second direction, a level of an upper surface of the first gate and a level of a lower surface of the first gate, and
 a maximum width of the third portion of the gate isolation is less than a maximum width of the first portion of the gate isolation, and less than a maximum width of the second portion of the gate isolation, each of the maximum width of the first portion, the maximum width of the second portion and the maximum width of the third portion being in the first direction. 
   
     
     
       22. The semiconductor device of  claim 21 , wherein the gate isolation contacts the first gate, the second gate, the third gate and the fourth gate. 
     
     
       23. The semiconductor device of  claim 21 , wherein the first width is greater than the second width. 
     
     
       24. The semiconductor device of  claim 21 , wherein each of the plurality of channel patterns has a fin shape. 
     
     
       25. The semiconductor device of  claim 21 , wherein a lowermost portion of the first gap is disposed lower than a topmost portion of the first channel pattern. 
     
     
       26. The semiconductor device of  claim 21 , wherein a lowermost portion of the gate isolation is disposed lower than the lower surface of the first gate. 
     
     
       27. The semiconductor device of  claim 21 , wherein the first gap is elliptically shaped. 
     
     
       28. The semiconductor device of  claim 21 , wherein each of the first gate and the second gate includes a side surface concave toward the first portion of the gate isolation. 
     
     
       29. The semiconductor device of  claim 21 , wherein each of the first insulating layer and the second insulating layer includes a side surface concave toward the third portion of the gate isolation. 
     
     
       30. The semiconductor device of  claim 21 , wherein the first gap is overlapped with the first gate and the third gate in the first direction. 
     
     
       31. The semiconductor device of  claim 21 , wherein the gate isolation further includes a third part disposed upper than the first part in the second direction, and
 a third width of the third part of the first portion of the gate isolation is smaller than the first width.   
     
     
       32. A semiconductor device comprising:
 a substrate;   a plurality of channel patterns disposed on the substrate, and including a first channel pattern and a second channel pattern;   a first gate disposed on the first channel pattern, and extending in a first direction;   a second gate disposed on the first channel pattern, and extending in the first direction;   a third gate disposed on the second channel pattern, extending in the first direction, and spaced apart from the first gate;   a fourth gate disposed on the second channel pattern, extending in the first direction, and spaced apart from the second gate;   a first insulating layer disposed between the first gate and the second gate;   
       a second insulating layer disposed between the third gate and the fourth gate;
 a gate isolation extending in a second direction that is perpendicular to the first direction, and disposed between the first gate and the third gate, between the first insulating layer and the second insulating layer and between the second gate and the fourth gate; 
 a first gap disposed in the gate isolation, and disposed between the first gate and the third gate; 
 a second gap disposed in the gate isolation, and disposed between the first insulating layer and the second insulating layer; and 
 a third gap disposed in the gate isolation, and disposed between the second gate and the fourth gate, 
 wherein the gate isolation includes a first portion disposed between the first gate and the third gate, a second portion disposed between the first insulating layer and the second insulating layer, a third portion disposed between the second gate and the fourth gate, and a fourth portion disposed between the first portion and the second portion, 
 the first portion of the gate isolation includes a first part and a second part disposed lower than the first part in a third direction that is a vertical direction and is perpendicular to the first direction and the second direction, 
 a first width of the first part of the first portion of the gate isolation is greater than a second width of the second part of the first portion of the gate isolation, each of the first width and the second width extending in the first direction, 
 the first part of the first portion of the gate isolation is halfway between, in the third direction, a level of an upper surface of the first gate and a level of a lower surface of the first gate, and 
 a maximum width of the fourth portion of the gate isolation is less than a maximum width of the first portion of the gate isolation, and less than a maximum width of the second portion of the gate isolation, each of the maximum width of the first portion, the maximum width of the second portion and the maximum width of the fourth portion being in the first direction. 
 
     
     
       33. The semiconductor device of  claim 32 , wherein the first gap, the second gap and the third gap are aligned in the second direction. 
     
     
       34. The semiconductor device of  claim 32 , wherein a maximum width of the second portion of the gate isolation is less than a maximum width of the first portion of the gate isolation, and less than a maximum width of the third portion of the gate isolation, each of the maximum width of the first portion, the maximum width of the second portion and the maximum width of the third portion being in the first direction. 
     
     
       35. The semiconductor device of  claim 32 , wherein the first gap is overlapped with the first gate and the third gate in the first direction. 
     
     
       36. The semiconductor device of  claim 32 , wherein the third gap is overlapped with the second gate and the fourth gate in the first direction. 
     
     
       37. The semiconductor device of  claim 32 , wherein the first gap is at a central portion of the first portion of the gate isolation in the first direction, the second gap is at a central portion of the second portion of the gate isolation in the first direction and the third gap is at a central portion of the third portion of the gate isolation in the first direction. 
     
     
       38. The semiconductor device of  claim 32 , wherein a width of the first portion along the first direction is maximum at a center of the first portion in the second direction. 
     
     
       39. The semiconductor device of  claim 32 , wherein the gate isolation further includes a fifth portion disposed between the second portion and the third portion, and
 a maximum width of the fifth portion of the gate isolation is less than a maximum width of the second portion of the gate isolation, and less than a maximum width of the third portion of the gate isolation, each of the maximum width of the second portion, the maximum width of the third portion and the maximum width of the fifth portion being in the first direction.   
     
     
       40. The semiconductor device of  claim 32 , wherein the first gap is elliptically shaped.