Assignee
FROHBERG KAI
DE·10 granted patents·13 pending applications·28 citations·filing 2005–2012
Top patents by PatentIndex Score
23 records- 0181US8470661B2High-K gate electrode structure formed after transistor fabrication by using a spacerFROHBERG KAI·Filed 2009·Granted Jun 25, 2013·8 cites·15 claims
- 0277US8492217B2Methods of forming conductive contacts with reduced dimensionsFROHBERG KAI·Filed 2011·Granted Jul 23, 2013·6 cites·11 claims
- 0373US8338284B2Stress engineering in a contact level of semiconductor devices by stressed conductive layers and an isolation spacerFROHBERG KAI·Filed 2010·Granted Dec 25, 2012·4 cites·15 claims
- 0471US8536050B2Selective shrinkage of contact elements in a semiconductor deviceFROHBERG KAI·Filed 2011·Granted Sep 17, 2013·3 cites·18 claims
- 0568US8105962B2Method and a semiconductor device comprising a protection layer for reducing stress relaxation in a dual stress liner approachFROHBERG KAI·Filed 2008·Granted Jan 31, 2012·3 cites·7 claims
- 0664US8609524B2Method for making semiconductor device comprising replacement gate electrode structures with an enhanced diffusion barrierFROHBERG KAI·Filed 2010·Granted Dec 17, 2013·3 cites·14 claims
- 0758US8658494B2Dual contact metallization including electroless plating in a semiconductor deviceFROHBERG KAI·Filed 2010·Granted Feb 25, 2014·1 cites·18 claims
- 0856US2010133621A1Restricted stress regions formed in the contact level of a semiconductor deviceFROHBERG KAI·Filed 2009·Application pending·0 cites
- 0947US2009108336A1Method for adjusting the height of a gate electrode in a semiconductor deviceFROHBERG KAI·Filed 2008·Application pending·0 cites
- 1046US2012091535A1Method and Semiconductor Device Comprising a Protection Layer for Reducing Stress Relaxation in a Dual Stress Liner ApproachFROHBERG KAI·Filed 2011·Application pending·0 cites
- 1145US2008265419A1Semiconductor structure comprising an electrically conductive feature and method of forming the sameFROHBERG KAI·Filed 2007·Application pending·0 cites
- 1244US2009294809A1Reduction of metal silicide diffusion in a semiconductor device by protecting sidewalls of an active regionFROHBERG KAI·Filed 2009·Application pending·0 cites
- 1344US2010055902A1Reducing critical dimensions of vias and contacts above the device level of semiconductor devicesFROHBERG KAI·Filed 2009·Application pending·0 cites
- 1443US9006114B2Method for selectively removing a spacer in a dual stress liner approachFROHBERG KAI·Filed 2009·Granted Apr 14, 2015·0 cites·22 claims
- 1543US8101524B2Technique for enhancing the fill capabilities in an electrochemical deposition process by edge rounding of trenchesFROHBERG KAI·Filed 2005·Granted Jan 24, 2012·0 cites·11 claims
- 1642US8941182B2Buried sublevel metallizations for improved transistor densityFROHBERG KAI·Filed 2011·Granted Jan 27, 2015·0 cites·17 claims
- 1742US2007096221A1Semiconductor device comprising copper-based contact plug and a method of forming the sameFROHBERG KAI·Filed 2006·Application pending·0 cites
- 1841US2006246718A1Technique for forming self-aligned vias in a metallization layerFROHBERG KAI·Filed 2005·Application pending·0 cites
- 1941US2006172518A1Method of patterning a layer of a materialFROHBERG KAI·Filed 2005·Application pending·0 cites
- 2039US2008054415A1n-channel field effect transistor having a contact etch stop layer in combination with an interlayer dielectric sub-layer having the same type of intrinsic stressFROHBERG KAI·Filed 2007·Application pending·0 cites
- 2137US2010301486A1High-aspect ratio contact element with superior shape in a semiconductor device for improving liner depositionFROHBERG KAI·Filed 2010·Application pending·0 cites
- 2237US2013189822A1Methods of fabricating integrated circuits with the elimination of voids in interlayer dielecticsFROHBERG KAI·Filed 2012·Application pending·0 cites
- 2335US2012115326A1Method of Forming Metal Silicide RegionsFROHBERG KAI·Filed 2010·Application pending·0 cites
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