Restricted stress regions formed in the contact level of a semiconductor device

Abstract

In sophisticated semiconductor devices, an efficient stress decoupling may be accomplished between neighboring transistor elements of a densely packed device region by providing a gap or a stress decoupling region between the corresponding transistors. For example, a gap may be formed in the stress-inducing material so as to reduce the mutual interaction of the stress-inducing material on the closely spaced transistor elements. In some illustrative aspects, the stress-inducing material may be provided as an island for each individual transistor element.

1 . A method, comprising:
 forming a stress-inducing layer above a first transistor and a second transistor formed in a device level of a semiconductor device; and   forming a stress decoupling region in said stress-inducing layer between said first and second transistors, said stress decoupling region extending along a transistor width direction of said first and second transistors.   
   
   
       2 . The method of  claim 1 , wherein forming said stress decoupling region comprises reducing a thickness of said stress-inducing layer between said first and second transistors. 
   
   
       3 . The method of  claim 2 , wherein said stress-inducing layer is substantially completely removed in said stress decoupling region. 
   
   
       4 . The method of  claim 1 , wherein said stress decoupling region laterally encloses said first transistor and said second transistor so as to provide a first island of stress-inducing material formed above said first transistor and a second island of stress-inducing material formed above said second transistor. 
   
   
       5 . The method of  claim 1 , wherein forming said stress decoupling region comprises locally modifying a surface condition at an area corresponding to said stress decoupling region so as to obtain a reduced deposition rate upon forming said stress-inducing layer. 
   
   
       6 . The method of  claim 2 , wherein reducing a thickness of said stress-inducing layer in said stress decoupling region comprises forming an etch mask that covers at least a portion of said first and second transistors and exposes said stress decoupling region. 
   
   
       7 . The method of  claim 6 , wherein said etch mask is formed so as to expose a portion of said stress-inducing layer formed above a third transistor. 
   
   
       8 . The method of  claim 6 , wherein forming said etch mask comprises forming a mask material on said stress-inducing layer, removing a portion of said mask material so as to expose a portion of said stress-inducing layer and performing a surface treatment in the presence of said mask material. 
   
   
       9 . The method of  claim 7 , further comprising removing said exposed portion of said stress-inducing layer and forming a second stress-inducing layer above said third transistor. 
   
   
       10 . The method of  claim 9 , further comprising removing said second stress-inducing layer from above said first and second transistors and from said stress decoupling region. 
   
   
       11 . The method of  claim 10 , wherein said stress-inducing layer and said second stress-inducing layer have a different type of internal stress. 
   
   
       12 . The method of  claim 1 , further comprising forming an interlayer dielectric material above said stress-inducing layer, wherein said interlayer dielectric material comprises a copper diffusion hindering material at least in said stress decoupling region. 
   
   
       13 . A method of inducing strain in transistors of a semiconductor device, the method comprising:
 forming a first stress-inducing layer above a first transistor and a second transistor; and   selectively removing said first stress-inducing layer from a region between said first and second transistors, said region extending at least along a width dimension of said first and second transistors.   
   
   
       14 . The method of  claim 13 , further comprising forming said first stress-inducing layer above a third transistor and removing said first stress-inducing layer from above said third transistor. 
   
   
       15 . The method of  claim 14 , wherein said first stress-inducing layer is removed from said region and from above said third transistor by performing a common etch process. 
   
   
       16 . The method of  claim 13 , further comprising forming a second stress-inducing layer above said first and second transistors and above a third transistor and removing said second stress-inducing layer from above said first and second transistors and from said region. 
   
   
       17 . The method of  claim 16 , wherein said first and second stress-inducing layers are removed from said region during the same etch process. 
   
   
       18 . The method of  claim 16 , wherein said first and second stress-inducing layers have different types of internal stress. 
   
   
       19 . The method of  claim 13 , further comprising forming an etch stop layer at least on a portion of said first stress-inducing layer. 
   
   
       20 . The method of  claim 19 , wherein said etch stop layer is formed so as to expose a second portion of said first stress-inducing layer that corresponds to said region. 
   
   
       21 . A semiconductor device, comprising:
 a first transistor comprising a first channel region;   a second transistor comprising a second channel region;   a stress-inducing layer formed above said first and second transistors, said stress-inducing layer inducing a specified type of strain in said first and second channel regions; and   a stress decoupling region formed laterally between said first and second transistors and extending at least along a width of said first and second transistors, said stress decoupling region representing a gap in said stress-inducing layer.   
   
   
       22 . The semiconductor device of  claim 21 , wherein said stress decoupling region extends along a transistor length direction. 
   
   
       23 . The semiconductor device of  claim 21 , further comprising a third transistor and a second stress-inducing layer formed above said third transistor, wherein said second stress-inducing layer induces a type of strain in a channel region of said third transistor that is different from said specified type of strain. 
   
   
       24 . The semiconductor device of  claim 22 , wherein a first portion of said first stress-inducing layer formed above said first transistor is isolated from a second portion of said first-stress inducing layer formed above said second transistor. 
   
   
       25 . The semiconductor device of  claim 21 , wherein a lateral distance between said gate electrodes of said first and second transistors is approximately 100 nm or less.