Inventor · disambiguated record
Thomas Werner
Also filed as: WERNER THOMAS · WERNER THOMAS R
61 granted patents·24 pending applications·745 citations·filing 1982–2016
98Inventor score
Files withGLOBALFOUNDRIES INC23ADVANCED MICRO DEVICES INC19WERNER THOMAS9FEUSTEL FRANK8FROHBERG KAI6
Top patents by PatentIndex Score
85 records- 0198US8048811B2Method for patterning a metallization layer by reducing resist strip induced damage of the dielectric materialADVANCED MICRO DEVICES INC·Filed 2009·Granted Nov 1, 2011·153 cites·24 claims
- 0296US6228758B1Method of making dual damascene conductive interconnections and integrated circuit device comprising sameADVANCED MICRO DEVICES INC·Filed 1998·Granted May 8, 2001·241 cites·12 claims
- 0390US8344474B2Microstructure device including a metallization structure with self-aligned air gaps and refilled air gap exclusion zonesADVANCED MICRO DEVICES INC·Filed 2010·Granted Jan 1, 2013·12 cites·21 claims
- 0489US7902581B2Semiconductor device comprising a contact structure based on copper and tungstenGLOBALFOUNDRIES INC·Filed 2006·Granted Mar 8, 2011·18 cites·37 claims
- 0588US7085300B2Integral vertical cavity surface emitting laser and power monitorFINISAR CORP·Filed 2001·Granted Aug 1, 2006·27 cites·25 claims
- 0686US8048796B2Microstructure device including a metallization structure with self-aligned air gaps formed based on a sacrificial materialGLOBALFOUNDRIES INC·Filed 2010·Granted Nov 1, 2011·9 cites·16 claims
- 0785US7977237B2Fabricating vias of different size of a semiconductor device by splitting the via patterning processGLOBALFOUNDRIES INC·Filed 2010·Granted Jul 12, 2011·7 cites·20 claims
- 0885US7932166B2Field effect transistor having a stressed contact etch stop layer with reduced conformalityADVANCED MICRO DEVICES INC·Filed 2007·Granted Apr 26, 2011·10 cites·22 claims
- 0985US7764078B2Test structure for monitoring leakage currents in a metallization layerGLOBALFOUNDRIES INC·Filed 2007·Granted Jul 27, 2010·10 cites·17 claims
- 1084US4454495ALayered ultra-thin coherent structures used as electrical resistors having low temperature coefficient of resistivityUS ENERGY·Filed 1982·Granted Jun 12, 1984·30 cites·8 claims
- 1183US8399352B2Semiconductor device comprising self-aligned contact bars and metal lines with increased via landing regionsWERNER THOMAS·Filed 2011·Granted Mar 19, 2013·6 cites·13 claims
- 1283US7800106B2Test structure for OPC-related shorts between lines in a semiconductor deviceADVANCED MICRO DEVICES INC·Filed 2007·Granted Sep 21, 2010·8 cites·16 claims
- 1382US8679924B2Self-aligned multiple gate transistor formed on a bulk substrateWEI ANDY·Filed 2011·Granted Mar 25, 2014·7 cites·14 claims
- 1482US6964874B2Void formation monitoring in a damascene processADVANCED MICRO DEVICES INC·Filed 2002·Granted Nov 15, 2005·30 cites·43 claims
- 1580US7705352B2Test structure for estimating electromigration effects with increased robustness with respect to barrier defects in viasGLOBALFOUNDRIES INC·Filed 2007·Granted Apr 27, 2010·6 cites·15 claims
- 1679US8377820B2Method of forming a metallization system of a semiconductor device by using a hard mask for defining the via sizeGLOBALFOUNDRIES INC·Filed 2010·Granted Feb 19, 2013·4 cites·24 claims
- 1778US8420533B2Metallization system of a semiconductor device comprising rounded interconnects formed by hard mask roundingSEIDEL ROBERT·Filed 2010·Granted Apr 16, 2013·4 cites·20 claims
- 1877US8357610B2Reducing patterning variability of trenches in metallization layer stacks with a low-k material by reducing contamination of trench dielectricsGLOBALFOUNDRIES INC·Filed 2009·Granted Jan 22, 2013·6 cites·21 claims
- 1976US9455232B2Semiconductor structure including a die seal leakage detection material, method for the formation thereof and method including a test of a semiconductor structureGLOBALFOUNDRIES INC·Filed 2014·Granted Sep 27, 2016·3 cites·16 claims
- 2075US8080866B23-D integrated semiconductor device comprising intermediate heat spreading capabilitiesWERNER THOMAS·Filed 2009·Granted Dec 20, 2011·5 cites·15 claims
- 2175US7871941B2Method for reducing resist poisoning during patterning of stressed nitrogen-containing layers in a semiconductor deviceADVANCED MICRO DEVICES INC·Filed 2007·Granted Jan 18, 2011·4 cites·19 claims
- 2275US7622391B2Method of forming an electrically conductive line in an integrated circuitADVANCED MICRO DEVICES INC·Filed 2007·Granted Nov 24, 2009·9 cites·16 claims
- 2373US8241973B2Method for increasing penetration depth of drain and source implantation species for a given gate heightGRIEBENOW UWE·Filed 2008·Granted Aug 14, 2012·3 cites·16 claims
- 2473US6893956B2Barrier layer for a copper metallization layer including a low-k dielectricADVANCED MICRO DEVICES INC·Filed 2003·Granted May 17, 2005·20 cites·41 claims
- 2572US8835303B2Metallization system of a semiconductor device comprising extra-tapered transition viasFEUSTEL FRANK·Filed 2009·Granted Sep 16, 2014·5 cites·25 claims
- 2672US5976948AProcess for forming an isolation region with trench capADVANCED MICRO DEVICES INC·Filed 1998·Granted Nov 2, 1999·40 cites·20 claims
- 2771US9245860B2Metallization system of a semiconductor device including metal pillars having a reduced diameter at the bottomFEUSTEL FRANK·Filed 2010·Granted Jan 26, 2016·3 cites·25 claims
- 2871US7989352B2Technique for reducing plasma-induced etch damage during the formation of vias in interlayer dielectricsADVANCED MICRO DEVICES INC·Filed 2007·Granted Aug 2, 2011·3 cites·13 claims
- 2969US8716126B2Semiconductor device comprising self-aligned contact bars and metal lines with increased via landing regionsGLOBALFOUNDRIES INC·Filed 2013·Granted May 6, 2014·2 cites·20 claims
- 3068US8105962B2Method and a semiconductor device comprising a protection layer for reducing stress relaxation in a dual stress liner approachFROHBERG KAI·Filed 2008·Granted Jan 31, 2012·3 cites·7 claims
- 3168US7462563B2Method of forming an etch indicator layer for reducing etch non-uniformitiesADVANCED MICRO DEVICES INC·Filed 2007·Granted Dec 9, 2008·2 cites·23 claims
- 3267US10014279B2Methods of forming 3-D integrated semiconductor devices having intermediate heat spreading capabilitiesGLOBALFOUNDRIES INC·Filed 2016·Granted Jul 3, 2018·1 cites·20 claims
- 3366US8482123B2Stress reduction in chip packaging by using a low-temperature chip-package connection regimeGRILLBERGER MICHAEL·Filed 2011·Granted Jul 9, 2013·2 cites·23 claims
- 3466US8216927B2Method of reducing contamination by providing a removable polymer protection film during microstructure processingRICHTER RALF·Filed 2011·Granted Jul 10, 2012·1 cites·15 claims
- 3566US7951677B2Corner rounding in a replacement gate approach based on a sacrificial fill material applied prior to work function metal depositionGLOBALFOUNDRIES INC·Filed 2010·Granted May 31, 2011·2 cites·20 claims
- 3666US6724096B2Die corner alignment structureADVANCED MICRO DEVICES INC·Filed 2002·Granted Apr 20, 2004·14 cites·18 claims
- 3764US8609524B2Method for making semiconductor device comprising replacement gate electrode structures with an enhanced diffusion barrierFROHBERG KAI·Filed 2010·Granted Dec 17, 2013·3 cites·14 claims
- 3864US7022602B2Nitrogen-enriched low-k barrier layer for a copper metallization layerADVANCED MICRO DEVICES INC·Filed 2003·Granted Apr 4, 2006·11 cites·17 claims
- 3962US9318468B23-D integrated semiconductor device comprising intermediate heat spreading capabilitiesWERNER THOMAS·Filed 2011·Granted Apr 19, 2016·1 cites·27 claims
- 4062US8368221B2Hybrid contact structure with low aspect ratio contacts in a semiconductor deviceADVANCED MICRO DEVICES INC·Filed 2008·Granted Feb 5, 2013·2 cites·24 claims
- 4162US8040497B2Method and test structure for estimating focus settings in a lithography process based on CD measurementsGLOBALFOUNDRIES INC·Filed 2007·Granted Oct 18, 2011·1 cites·16 claims
- 4262US8030209B2Enhancing structural integrity of low-k dielectrics in metallization systems of semiconductor devices by using a crack suppressing material layerGLOBALFOUNDDRIES INC·Filed 2009·Granted Oct 4, 2011·2 cites·24 claims
- 4361US8652341B2Method and apparatus for structuring components made of a material composed of silicon oxideGESSNER THOMAS·Filed 2009·Granted Feb 18, 2014·2 cites·10 claims
- 4461US8198147B2Superior fill conditions in a replacement gate approach by using a tensile stressed overlayerFEUSTEL FRANK·Filed 2010·Granted Jun 12, 2012·1 cites·19 claims
- 4558US9349641B2Wafer with improved plating current distributionGLOBALFOUNDRIES INC·Filed 2014·Granted May 24, 2016·0 cites·18 claims
- 4658US8048736B2Semiconductor device comprising a capacitor in the metallization system and a method of forming the capacitorADVANCED MICRO DEVICES INC·Filed 2008·Granted Nov 1, 2011·1 cites·17 claims
- 4756US2010133621A1Restricted stress regions formed in the contact level of a semiconductor deviceFROHBERG KAI·Filed 2009·Application pending·0 cites
- 4855US10711311B2Genomic rearrangements associated with prostate cancer and methods of using the sameHENRY M JACKSON FOUND ADVANCEMENT MILITARY MEDICINE INC·Filed 2014·Granted Jul 14, 2020·0 cites·6 claims
- 4954US9627317B2Wafer with improved plating current distributionGLOBALFOUNDRIES INC·Filed 2016·Granted Apr 18, 2017·0 cites·18 claims
- 5054US8828887B2Restricted stress regions formed in the contact level of a semiconductor deviceGLOBALFOUNDRIES INC·Filed 2012·Granted Sep 9, 2014·0 cites·17 claims
Showing the top 50 of 85 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →