Inventor · disambiguated record
Kai Frohberg
Also filed as: FROHBERG KAI
90 granted patents·33 pending applications·1,220 citations·filing 2005–2015
99Inventor score
Files withADVANCED MICRO DEVICES INC33GLOBALFOUNDRIES INC27FROHBERG KAI23GRIEBENOW UWE8FEUSTEL FRANK7
Top patents by PatentIndex Score
123 records- 0197US8110487B2Method of creating a strained channel region in a transistor by deep implantation of strain-inducing species below the channel regionGRIEBENOW UWE·Filed 2008·Granted Feb 7, 2012·104 cites·20 claims
- 0297US7550396B2Method for reducing resist poisoning during patterning of silicon nitride layers in a semiconductor deviceADVANCED MICRO DEVICES INC·Filed 2007·Granted Jun 23, 2009·507 cites·22 claims
- 0397US7259091B2Technique for forming a passivation layer prior to depositing a barrier layer in a copper metallization layerADVANCED MICRO DEVICES INC·Filed 2005·Granted Aug 21, 2007·268 cites·10 claims
- 0493US7396718B2Technique for creating different mechanical strain in different channel regions by forming an etch stop layer stack having differently modified intrinsic stressADVANCED MICRO DEVICES INC·Filed 2005·Granted Jul 8, 2008·29 cites·9 claims
- 0593US7314793B2Technique for controlling mechanical stress in a channel region by spacer removalADVANCED MICRO DEVICES INC·Filed 2005·Granted Jan 1, 2008·39 cites·14 claims
- 0689US7902581B2Semiconductor device comprising a contact structure based on copper and tungstenGLOBALFOUNDRIES INC·Filed 2006·Granted Mar 8, 2011·18 cites·37 claims
- 0788US7517816B2Technique for creating different mechanical stress in different channel regions by forming an etch stop layer having differently modified intrinsic stressADVANCED MICRO DEVICES INC·Filed 2005·Granted Apr 14, 2009·17 cites·6 claims
- 0888US7491555B2Method and semiconductor structure for monitoring the fabrication of interconnect structures and contacts in a semiconductor deviceADVANCED MICRO DEVICES INC·Filed 2006·Granted Feb 17, 2009·17 cites·19 claims
- 0986US8367504B2Method for forming semiconductor fuses in a semiconductor device comprising metal gatesGLOBALFOUNDRIES INC·Filed 2010·Granted Feb 5, 2013·6 cites·12 claims
- 1085US7977237B2Fabricating vias of different size of a semiconductor device by splitting the via patterning processGLOBALFOUNDRIES INC·Filed 2010·Granted Jul 12, 2011·7 cites·20 claims
- 1185US7932166B2Field effect transistor having a stressed contact etch stop layer with reduced conformalityADVANCED MICRO DEVICES INC·Filed 2007·Granted Apr 26, 2011·10 cites·22 claims
- 1283US7800106B2Test structure for OPC-related shorts between lines in a semiconductor deviceADVANCED MICRO DEVICES INC·Filed 2007·Granted Sep 21, 2010·8 cites·16 claims
- 1382US7838359B2Technique for forming contact insulation layers and silicide regions with different characteristicsADVANCED MICRO DEVICES INC·Filed 2006·Granted Nov 23, 2010·10 cites·13 claims
- 1481US8470661B2High-K gate electrode structure formed after transistor fabrication by using a spacerFROHBERG KAI·Filed 2009·Granted Jun 25, 2013·8 cites·15 claims
- 1580US7705352B2Test structure for estimating electromigration effects with increased robustness with respect to barrier defects in viasGLOBALFOUNDRIES INC·Filed 2007·Granted Apr 27, 2010·6 cites·15 claims
- 1680US7381602B2Method of forming a field effect transistor comprising a stressed channel regionADVANCED MICRO DEVICES INC·Filed 2005·Granted Jun 3, 2008·9 cites·39 claims
- 1779US8615145B2Semiconductor device comprising a buried waveguide for device internal optical communicationGRIEBENOW UWE·Filed 2010·Granted Dec 24, 2013·2 cites·19 claims
- 1879US8377820B2Method of forming a metallization system of a semiconductor device by using a hard mask for defining the via sizeGLOBALFOUNDRIES INC·Filed 2010·Granted Feb 19, 2013·4 cites·24 claims
- 1979US7871877B2Technique for strain engineering in silicon-based transistors by using implantation techniques for forming a strain-inducing layer under the channel regionGLOBALFOUNDRIES INC·Filed 2008·Granted Jan 18, 2011·6 cites·18 claims
- 2077US8492217B2Methods of forming conductive contacts with reduced dimensionsFROHBERG KAI·Filed 2011·Granted Jul 23, 2013·6 cites·11 claims
- 2177US8357610B2Reducing patterning variability of trenches in metallization layer stacks with a low-k material by reducing contamination of trench dielectricsGLOBALFOUNDRIES INC·Filed 2009·Granted Jan 22, 2013·6 cites·21 claims
- 2275US8786088B2Semiconductor device including ultra low-K (ULK) metallization stacks with reduced chip-package interactionHUISINGA TORSTEN·Filed 2010·Granted Jul 22, 2014·4 cites·12 claims
- 2375US7871941B2Method for reducing resist poisoning during patterning of stressed nitrogen-containing layers in a semiconductor deviceADVANCED MICRO DEVICES INC·Filed 2007·Granted Jan 18, 2011·4 cites·19 claims
- 2475US7622391B2Method of forming an electrically conductive line in an integrated circuitADVANCED MICRO DEVICES INC·Filed 2007·Granted Nov 24, 2009·9 cites·16 claims
- 2575US7556996B2Field effect transistor comprising a stressed channel region and method of forming the sameADVANCED MICRO DEVICES INC·Filed 2007·Granted Jul 7, 2009·7 cites·6 claims
- 2674US8318598B2Contacts and vias of a semiconductor device formed by a hard mask and double exposureBEYER SVEN·Filed 2009·Granted Nov 27, 2012·6 cites·25 claims
- 2774US7741191B2Method for preventing the formation of electrical shorts via contact ILD voidsGLOBALFOUNDRIES INC·Filed 2007·Granted Jun 22, 2010·6 cites·12 claims
- 2874US7482219B2Technique for creating different mechanical strain by a contact etch stop layer stack with an intermediate etch stop layerADVANCED MICRO DEVICES INC·Filed 2006·Granted Jan 27, 2009·6 cites·21 claims
- 2973US8338284B2Stress engineering in a contact level of semiconductor devices by stressed conductive layers and an isolation spacerFROHBERG KAI·Filed 2010·Granted Dec 25, 2012·4 cites·15 claims
- 3073US8241973B2Method for increasing penetration depth of drain and source implantation species for a given gate heightGRIEBENOW UWE·Filed 2008·Granted Aug 14, 2012·3 cites·16 claims
- 3172US8859398B2Enhancing adhesion of interlayer dielectric materials of semiconductor devices by suppressing silicide formation at the substrate edgeLETZ TOBIAS·Filed 2010·Granted Oct 14, 2014·3 cites·29 claims
- 3272US8835303B2Metallization system of a semiconductor device comprising extra-tapered transition viasFEUSTEL FRANK·Filed 2009·Granted Sep 16, 2014·5 cites·25 claims
- 3372US7713815B2Semiconductor device including a vertical decoupling capacitorGLOBALFOUNDRIES INC·Filed 2006·Granted May 11, 2010·5 cites·9 claims
- 3471US9245860B2Metallization system of a semiconductor device including metal pillars having a reduced diameter at the bottomFEUSTEL FRANK·Filed 2010·Granted Jan 26, 2016·3 cites·25 claims
- 3571US8536050B2Selective shrinkage of contact elements in a semiconductor deviceFROHBERG KAI·Filed 2011·Granted Sep 17, 2013·3 cites·18 claims
- 3671US8129276B2Void sealing in a dielectric material of a contact level of a semiconductor device comprising closely spaced transistorsRICHTER RALF·Filed 2010·Granted Mar 6, 2012·3 cites·11 claims
- 3771US7989352B2Technique for reducing plasma-induced etch damage during the formation of vias in interlayer dielectricsADVANCED MICRO DEVICES INC·Filed 2007·Granted Aug 2, 2011·3 cites·13 claims
- 3870US8440534B2Threshold adjustment for MOS devices by adapting a spacer width prior to implantationGRIEBENOW UWE·Filed 2011·Granted May 14, 2013·2 cites·17 claims
- 3970US8384161B2Contact optimization for enhancing stress transfer in closely spaced transistorsGLOBALFOUNDRIES INC·Filed 2010·Granted Feb 26, 2013·3 cites·26 claims
- 4069US8877597B2Embedding metal silicide contact regions reliably into highly doped drain and source regions by a stop implantationHEINRICH JENS·Filed 2011·Granted Nov 4, 2014·2 cites·17 claims
- 4169US8772178B2Technique for forming a dielectric interlayer above a structure including closely spaced linesRUELKE HARTMUT·Filed 2005·Granted Jul 8, 2014·5 cites·29 claims
- 4269US7763532B2Technique for forming a dielectric etch stop layer above a structure including closely spaced linesADVANCED MICRO DEVICES INC·Filed 2005·Granted Jul 27, 2010·4 cites·31 claims
- 4369US7442638B2Method for forming a tungsten interconnect structure with enhanced sidewall coverage of the barrier layerADVANCED MICRO DEVICES INC·Filed 2006·Granted Oct 28, 2008·4 cites·16 claims
- 4468US8105962B2Method and a semiconductor device comprising a protection layer for reducing stress relaxation in a dual stress liner approachFROHBERG KAI·Filed 2008·Granted Jan 31, 2012·3 cites·7 claims
- 4568US7462563B2Method of forming an etch indicator layer for reducing etch non-uniformitiesADVANCED MICRO DEVICES INC·Filed 2007·Granted Dec 9, 2008·2 cites·23 claims
- 4667US8859418B2Methods of forming conductive structures using a dual metal hard mask techniqueHUISINGA TORSTEN·Filed 2012·Granted Oct 14, 2014·2 cites·16 claims
- 4767US7279415B2Method for forming a metallization layer stack to reduce the roughness of metal linesADVANCED MICRO DEVICES INC·Filed 2005·Granted Oct 9, 2007·2 cites·16 claims
- 4866US8492269B2Hybrid contact structure with low aspect ratio contacts in a semiconductor deviceHEINRICH JENS·Filed 2011·Granted Jul 23, 2013·2 cites·15 claims
- 4966US8216927B2Method of reducing contamination by providing a removable polymer protection film during microstructure processingRICHTER RALF·Filed 2011·Granted Jul 10, 2012·1 cites·15 claims
- 5066US7341903B2Method of forming a field effect transistor having a stressed channel regionADVANCED MICRO DEVICES INC·Filed 2005·Granted Mar 11, 2008·3 cites·14 claims
Showing the top 50 of 123 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →