Inventor · disambiguated record
Frank Feustel
Also filed as: FEUSTEL FRANK
53 granted patents·31 pending applications·333 citations·filing 2005–2016
98Inventor score
Files withGLOBALFOUNDRIES INC19FEUSTEL FRANK15ADVANCED MICRO DEVICES INC12WERNER THOMAS9FROHBERG KAI6
Top patents by PatentIndex Score
84 records- 0198US8048811B2Method for patterning a metallization layer by reducing resist strip induced damage of the dielectric materialADVANCED MICRO DEVICES INC·Filed 2009·Granted Nov 1, 2011·153 cites·24 claims
- 0290US7928004B2Nano imprint technique with increased flexibility with respect to alignment and feature shapingADVANCED MICRO DEVICES INC·Filed 2007·Granted Apr 19, 2011·16 cites·6 claims
- 0385US8399335B2Sophisticated metallization systems in semiconductors formed by removing damaged dielectric layers after forming the metal featuresHUISINGA TORSTEN·Filed 2010·Granted Mar 19, 2013·9 cites·18 claims
- 0485US7977237B2Fabricating vias of different size of a semiconductor device by splitting the via patterning processGLOBALFOUNDRIES INC·Filed 2010·Granted Jul 12, 2011·7 cites·20 claims
- 0585US7932166B2Field effect transistor having a stressed contact etch stop layer with reduced conformalityADVANCED MICRO DEVICES INC·Filed 2007·Granted Apr 26, 2011·10 cites·22 claims
- 0685US7764078B2Test structure for monitoring leakage currents in a metallization layerGLOBALFOUNDRIES INC·Filed 2007·Granted Jul 27, 2010·10 cites·17 claims
- 0783US8399352B2Semiconductor device comprising self-aligned contact bars and metal lines with increased via landing regionsWERNER THOMAS·Filed 2011·Granted Mar 19, 2013·6 cites·13 claims
- 0883US8293641B2Nano imprint technique with increased flexibility with respect to alignment and feature shapingSEIDEL ROBERT·Filed 2011·Granted Oct 23, 2012·6 cites·6 claims
- 0983US7800106B2Test structure for OPC-related shorts between lines in a semiconductor deviceADVANCED MICRO DEVICES INC·Filed 2007·Granted Sep 21, 2010·8 cites·16 claims
- 1080US7705352B2Test structure for estimating electromigration effects with increased robustness with respect to barrier defects in viasGLOBALFOUNDRIES INC·Filed 2007·Granted Apr 27, 2010·6 cites·15 claims
- 1179US8377820B2Method of forming a metallization system of a semiconductor device by using a hard mask for defining the via sizeGLOBALFOUNDRIES INC·Filed 2010·Granted Feb 19, 2013·4 cites·24 claims
- 1277US8357610B2Reducing patterning variability of trenches in metallization layer stacks with a low-k material by reducing contamination of trench dielectricsGLOBALFOUNDRIES INC·Filed 2009·Granted Jan 22, 2013·6 cites·21 claims
- 1377US8193086B2Local silicidation of via bottoms in metallization systems of semiconductor devicesLETZ TOBIAS·Filed 2009·Granted Jun 5, 2012·8 cites·21 claims
- 1476US9455232B2Semiconductor structure including a die seal leakage detection material, method for the formation thereof and method including a test of a semiconductor structureGLOBALFOUNDRIES INC·Filed 2014·Granted Sep 27, 2016·3 cites·16 claims
- 1575US8786088B2Semiconductor device including ultra low-K (ULK) metallization stacks with reduced chip-package interactionHUISINGA TORSTEN·Filed 2010·Granted Jul 22, 2014·4 cites·12 claims
- 1675US8080866B23-D integrated semiconductor device comprising intermediate heat spreading capabilitiesWERNER THOMAS·Filed 2009·Granted Dec 20, 2011·5 cites·15 claims
- 1774US7879709B2Semiconductor structure comprising an electrically conductive feature and method of forming a semiconductor structureGLOBALFOUNDRIES INC·Filed 2008·Granted Feb 1, 2011·6 cites·18 claims
- 1874US7741191B2Method for preventing the formation of electrical shorts via contact ILD voidsGLOBALFOUNDRIES INC·Filed 2007·Granted Jun 22, 2010·6 cites·12 claims
- 1973US8241973B2Method for increasing penetration depth of drain and source implantation species for a given gate heightGRIEBENOW UWE·Filed 2008·Granted Aug 14, 2012·3 cites·16 claims
- 2073US7306976B2Technique for enhancing thermal and mechanical characteristics of an underfill material of a substrate/die assemblyADVANCED MICRO DEVICES INC·Filed 2005·Granted Dec 11, 2007·5 cites·18 claims
- 2172US8859398B2Enhancing adhesion of interlayer dielectric materials of semiconductor devices by suppressing silicide formation at the substrate edgeLETZ TOBIAS·Filed 2010·Granted Oct 14, 2014·3 cites·29 claims
- 2272US8835303B2Metallization system of a semiconductor device comprising extra-tapered transition viasFEUSTEL FRANK·Filed 2009·Granted Sep 16, 2014·5 cites·25 claims
- 2372US7915170B2Reducing contamination of semiconductor substrates during beol processing by providing a protection layer at the substrate edgeADVANCED MICRO DEVICES INC·Filed 2007·Granted Mar 29, 2011·5 cites·17 claims
- 2471US9245860B2Metallization system of a semiconductor device including metal pillars having a reduced diameter at the bottomFEUSTEL FRANK·Filed 2010·Granted Jan 26, 2016·3 cites·25 claims
- 2571US8173538B2Method of selectively forming a conductive barrier layer by ALDFEUSTEL FRANK·Filed 2007·Granted May 8, 2012·6 cites·11 claims
- 2671US7989352B2Technique for reducing plasma-induced etch damage during the formation of vias in interlayer dielectricsADVANCED MICRO DEVICES INC·Filed 2007·Granted Aug 2, 2011·3 cites·13 claims
- 2770US8440534B2Threshold adjustment for MOS devices by adapting a spacer width prior to implantationGRIEBENOW UWE·Filed 2011·Granted May 14, 2013·2 cites·17 claims
- 2869US8877597B2Embedding metal silicide contact regions reliably into highly doped drain and source regions by a stop implantationHEINRICH JENS·Filed 2011·Granted Nov 4, 2014·2 cites·17 claims
- 2969US8716126B2Semiconductor device comprising self-aligned contact bars and metal lines with increased via landing regionsGLOBALFOUNDRIES INC·Filed 2013·Granted May 6, 2014·2 cites·20 claims
- 3068US8105962B2Method and a semiconductor device comprising a protection layer for reducing stress relaxation in a dual stress liner approachFROHBERG KAI·Filed 2008·Granted Jan 31, 2012·3 cites·7 claims
- 3168US7462563B2Method of forming an etch indicator layer for reducing etch non-uniformitiesADVANCED MICRO DEVICES INC·Filed 2007·Granted Dec 9, 2008·2 cites·23 claims
- 3267US10014279B2Methods of forming 3-D integrated semiconductor devices having intermediate heat spreading capabilitiesGLOBALFOUNDRIES INC·Filed 2016·Granted Jul 3, 2018·1 cites·20 claims
- 3367US8039398B2Method of reducing non-uniformities during chemical mechanical polishing of excess metal in a metallization level of microstructure devicesGLOBALFOUNDRIES INC·Filed 2007·Granted Oct 18, 2011·2 cites·22 claims
- 3466US8216927B2Method of reducing contamination by providing a removable polymer protection film during microstructure processingRICHTER RALF·Filed 2011·Granted Jul 10, 2012·1 cites·15 claims
- 3564US8323989B2Test system and method of reducing damage in seed layers in metallization systems of semiconductor devicesFEUSTEL FRANK·Filed 2010·Granted Dec 4, 2012·2 cites·15 claims
- 3662US9318468B23-D integrated semiconductor device comprising intermediate heat spreading capabilitiesWERNER THOMAS·Filed 2011·Granted Apr 19, 2016·1 cites·27 claims
- 3762US8368221B2Hybrid contact structure with low aspect ratio contacts in a semiconductor deviceADVANCED MICRO DEVICES INC·Filed 2008·Granted Feb 5, 2013·2 cites·24 claims
- 3862US8040497B2Method and test structure for estimating focus settings in a lithography process based on CD measurementsGLOBALFOUNDRIES INC·Filed 2007·Granted Oct 18, 2011·1 cites·16 claims
- 3962US8030209B2Enhancing structural integrity of low-k dielectrics in metallization systems of semiconductor devices by using a crack suppressing material layerGLOBALFOUNDDRIES INC·Filed 2009·Granted Oct 4, 2011·2 cites·24 claims
- 4061US8198147B2Superior fill conditions in a replacement gate approach by using a tensile stressed overlayerFEUSTEL FRANK·Filed 2010·Granted Jun 12, 2012·1 cites·19 claims
- 4158US9349641B2Wafer with improved plating current distributionGLOBALFOUNDRIES INC·Filed 2014·Granted May 24, 2016·0 cites·18 claims
- 4258US8048736B2Semiconductor device comprising a capacitor in the metallization system and a method of forming the capacitorADVANCED MICRO DEVICES INC·Filed 2008·Granted Nov 1, 2011·1 cites·17 claims
- 4356US2010133621A1Restricted stress regions formed in the contact level of a semiconductor deviceFROHBERG KAI·Filed 2009·Application pending·0 cites
- 4454US9627317B2Wafer with improved plating current distributionGLOBALFOUNDRIES INC·Filed 2016·Granted Apr 18, 2017·0 cites·18 claims
- 4554US8828887B2Restricted stress regions formed in the contact level of a semiconductor deviceGLOBALFOUNDRIES INC·Filed 2012·Granted Sep 9, 2014·0 cites·17 claims
- 4654US8174010B2Unified test structure for stress migration testsFEUSTEL FRANK·Filed 2007·Granted May 8, 2012·1 cites·19 claims
- 4754US7955962B2Method of reducing contamination by providing a removable polymer protection film during microstructure processingGLOBALFOUNDRIES INC·Filed 2007·Granted Jun 7, 2011·0 cites·24 claims
- 4854US2009321850A1Threshold adjustment for MOS devices by adapting a spacer width prior to implantationGRIEBENOW UWE·Filed 2009·Application pending·0 cites
- 4952US2009181537A1Semiconductor structure comprising an electrical connection and method of forming the sameADVANCED MICRO DEVICES INC·Filed 2009·Application pending·0 cites
- 5051US8735237B2Method for increasing penetration depth of drain and source implantation species for a given gate heightGRIEBENOW UWE·Filed 2012·Granted May 27, 2014·0 cites·22 claims
Showing the top 50 of 84 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →