Threshold adjustment for MOS devices by adapting a spacer width prior to implantation

Abstract

Different threshold voltages of transistors of the same conductivity type in a complex integrated circuit may be adjusted on the basis of different Miller capacitances, which may be accomplished by appropriately adapting a spacer width and/or performing a tilted extension implantation. Thus, efficient process strategies may be available to controllably adjust the Miller capacitance, thereby providing enhanced transistor performance of low threshold transistors while not unduly contributing to process complexity compared to conventional approaches in which threshold voltage values may be adjusted on the basis of complex halo and well doping regimes.

1 . A method, comprising:
 forming a spacer layer above a first structure formed above a first active region of a semiconductor device and a second structure formed above a second active region, said first and second structures representing at least one of a gate electrode and a gate place holder structure of a first transistor and a second transistor, respectively, said first transistor receiving a first threshold voltage and said second transistor receiving a second threshold voltage that is higher than said first threshold voltage;   forming a first spacer element on sidewalls of said first structure and a second spacer element on sidewalls of said second structure, said first spacer element having a first width that is less than a second width of said second spacer element; and   performing an implantation sequence on the basis of said first and second structures and said first and second spacer elements to form drain and source regions in said first and second active regions.   
   
   
       2 . The method of  claim 1 , wherein forming said first and second spacer elements comprises performing a first etch process to form said first and second spacer elements to have substantially the second width, and performing a second etch process to selectively remove material of said first spacer element to obtain said first width. 
   
   
       3 . The method of  claim 2 , wherein said second etch process is performed by using a plasma ambient. 
   
   
       4 . The method of  claim 2 , wherein said second etch process is performed by using a wet chemical etch ambient. 
   
   
       5 . The method of  claim 1 , wherein forming said first and second spacer elements comprises performing an ion bombardment selectively on a portion of said spacer layer located above said first active region and performing an etch process to form said first and second spacer elements. 
   
   
       6 . The method of  claim 5 , wherein performing said ion bombardment comprises performing an ion implantation process using a xenon species. 
   
   
       7 . The method of  claim 1 , wherein forming said first and second spacer elements comprises performing a first etch process to selectively reduce a thickness of said spacer layer above said first active region and performing a second etch process for forming said first and second spacer elements. 
   
   
       8 . The method of  claim 1 , further comprising forming said spacer layer above a third active region having formed thereon a third structure representing one of a gate electrode and a gate place holder structure of a third transistor, wherein said third transistor receives a third threshold voltage that is higher than said first and second threshold voltages. 
   
   
       9 . The method of  claim 8 , further comprising forming a third spacer element on sidewalls of said third structure, wherein said third spacer element has a third width that is greater than said second width. 
   
   
       10 . A method, comprising:
 selectively introducing a first dopant species into a first active region by performing a first implantation process while masking a second active region, said first active region having formed thereon one of a first gate electrode structure and a first gate place holder structure of a first transistor, said second active region having formed thereon one of a second gate electrode structure and a second gate place holder structure of a second transistor, said first and second transistors representing the same conductivity type; and   introducing a second dopant species at least into said second active region by a second implantation process, said first and second dopant species creating the same conductivity, said first and second implantation processes differing at least in a tilt angle.   
   
   
       11 . The method of  claim 10 , wherein said first transistor has a first threshold voltage and said second transistor has a second threshold voltage that is higher than said first threshold voltage and wherein said first implantation process is performed under a tilt angle that is greater than a tilt angle of said second implantation process. 
   
   
       12 . The method of  claim 11 , wherein said second implantation process is performed commonly for said first and second active regions. 
   
   
       13 . The method of  claim 10 , wherein said first implantation process is performed prior to said second implantation process. 
   
   
       14 . The method of  claim 10 , wherein said first implantation process is performed after said second implantation process. 
   
   
       15 . The method of  claim 11 , further comprising selectively reducing a width of said one of a first gate electrode structure and a first place holder structure. 
   
   
       16 . The method of  claim 15 , further comprising forming a mask covering said second active region and exposing said first active region, wherein said first implantation process and an etch process for reducing a width of said one of a first gate electrode structure and a first place holder structure are performed by using said mask. 
   
   
       17 . The method of  claim 16 , wherein reducing a width of said one of a first gate electrode structure and a first place holder structure is performed after performing said first implantation process. 
   
   
       18 . The method of  claim 10 , further comprising performing a third implantation process to introduce a third dopant species creating the same conductivity type in a third active region, wherein said third implantation process is performed by using a tilt angle that differs from a tilt angle used in said first and second implantation processes. 
   
   
       19 . A semiconductor device, comprising:
 a first transistor of a first conductivity type having a first threshold voltage and comprising a first gate electrode structure comprising a first sidewall spacer structure having a first width; and   a second transistor of said first conductivity type having a second threshold voltage that is higher than said first threshold voltage, said second transistor comprising a second gate electrode structure comprising a second sidewall spacer structure having a second width that is greater than said first width.   
   
   
       20 . The semiconductor of  claim 19 , further comprising a third transistor of said first conductivity type and having a third threshold voltage that is higher than said second threshold voltage, wherein said third transistor comprises a third gate electrode structure comprising a third sidewall spacer having a width that is greater than said second width.