Inventor · disambiguated record
Katrin Reiche
Also filed as: REICHE KATRIN
13 granted patents·5 pending applications·35 citations·filing 2008–2015
88Inventor score
Top patents by PatentIndex Score
18 records- 0181US8497583B2Stress reduction in chip packaging by a stress compensation region formed around the chipCHUMAKOV DMYTRO·Filed 2010·Granted Jul 30, 2013·7 cites·13 claims
- 0281US8470661B2High-K gate electrode structure formed after transistor fabrication by using a spacerFROHBERG KAI·Filed 2009·Granted Jun 25, 2013·8 cites·15 claims
- 0377US8492217B2Methods of forming conductive contacts with reduced dimensionsFROHBERG KAI·Filed 2011·Granted Jul 23, 2013·6 cites·11 claims
- 0474US8318598B2Contacts and vias of a semiconductor device formed by a hard mask and double exposureBEYER SVEN·Filed 2009·Granted Nov 27, 2012·6 cites·25 claims
- 0571US8536050B2Selective shrinkage of contact elements in a semiconductor deviceFROHBERG KAI·Filed 2011·Granted Sep 17, 2013·3 cites·18 claims
- 0670US8440534B2Threshold adjustment for MOS devices by adapting a spacer width prior to implantationGRIEBENOW UWE·Filed 2011·Granted May 14, 2013·2 cites·17 claims
- 0765US9590056B2Semiconductor device comprising contact structures with protection layers formed on sidewalls of contact etch stop layersGLOBALFOUNDRIES INC·Filed 2015·Granted Mar 7, 2017·1 cites·20 claims
- 0860US8536052B2Semiconductor device comprising contact elements with silicided sidewall regionsHEINRICH JENS·Filed 2011·Granted Sep 17, 2013·1 cites·15 claims
- 0960US8361844B2Method for adjusting the height of a gate electrode in a semiconductor deviceGLOBALFOUNDRIES INC·Filed 2010·Granted Jan 29, 2013·1 cites·20 claims
- 1054US2009321850A1Threshold adjustment for MOS devices by adapting a spacer width prior to implantationGRIEBENOW UWE·Filed 2009·Application pending·0 cites
- 1153US9269809B2Methods for forming protection layers on sidewalls of contact etch stop layersGLOBALFOUNDRIES INC·Filed 2014·Granted Feb 23, 2016·0 cites·23 claims
- 1251US8883582B2High-K gate electrode structure formed after transistor fabrication by using a spacerADVANCED MICRO DEVICES INC·Filed 2013·Granted Nov 11, 2014·0 cites·17 claims
- 1347US2009108336A1Method for adjusting the height of a gate electrode in a semiconductor deviceFROHBERG KAI·Filed 2008·Application pending·0 cites
- 1445US8349744B2Double deposition of a stress-inducing layer in an interlayer dielectric with intermediate stress relaxation in a semiconductor deviceADVANCED MICRO DEVICES INC·Filed 2008·Granted Jan 8, 2013·0 cites·13 claims
- 1544US2009294868A1Drive current adjustment for transistors formed in the same active region by locally inducing different lateral strain levels in the active regionGRIEBENOW UWE·Filed 2009·Application pending·0 cites
- 1642US8941182B2Buried sublevel metallizations for improved transistor densityFROHBERG KAI·Filed 2011·Granted Jan 27, 2015·0 cites·17 claims
- 1737US2013189822A1Methods of fabricating integrated circuits with the elimination of voids in interlayer dielecticsFROHBERG KAI·Filed 2012·Application pending·0 cites
- 1835US2012115326A1Method of Forming Metal Silicide RegionsFROHBERG KAI·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →